Condensed router headers with low latency output port calculation
First Claim
1. A method for communicating among cores in a multi-core processor device that comprises a plurality of cores, each core comprising a processor and a switch, the method comprising:
- routing a packet that includes a header and payload from an origin core to a destination core over a route including multiple cores in the multi-core processor device; and
at each core in the route before the destination core, routing the packet to the next core in the route according to a value of a respective symbol in a sequence of multiple symbols in the header, with the respective symbol having a first symbol value indicating a single likely direction, and the respective symbol having a second, different symbol value indicating routing according to at least one of multiple less likely routing directions.
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Accused Products
Abstract
Communicating among cores in a computing system comprising a plurality of cores, each core comprising a processor and a switch, includes: routing a packet from an origin core to a destination core over a route including multiple cores; and at each core in the route before the destination core, routing the packet to the next core in the route according to a respective symbol in a sequence of multiple symbols. The respective symbol has a first symbol value indicating a single likely direction and the respective symbol has a second symbol value indicating multiple less likely directions.
44 Citations
26 Claims
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1. A method for communicating among cores in a multi-core processor device that comprises a plurality of cores, each core comprising a processor and a switch, the method comprising:
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routing a packet that includes a header and payload from an origin core to a destination core over a route including multiple cores in the multi-core processor device; and at each core in the route before the destination core, routing the packet to the next core in the route according to a value of a respective symbol in a sequence of multiple symbols in the header, with the respective symbol having a first symbol value indicating a single likely direction, and the respective symbol having a second, different symbol value indicating routing according to at least one of multiple less likely routing directions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computer program product tangibly stored on a computer-readable hardware storage device, the computer program for communicating among cores in a multi-core processor device that comprises a plurality of cores, each core comprising a processor and a switch, the computer program including instructions for causing the computing system to:
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route a packet that includes a header and payload from an origin core to a destination core over a route including multiple cores in the multi-core processor device; and at each core in the route before the destination core, route the packet to the next core in the route according to a value of a respective symbol in a sequence of multiple symbols in the header, with the respective symbol having a first symbol value indicating a single likely direction and the respective symbol having a second, different symbol value indicating routing according to at least one of multiple less likely routing directions. - View Dependent Claims (13, 15, 16, 17)
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12. A computing system, comprising:
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a multi-core processor device that comprises a plurality of cores, with each of the cores comprising a switch and a processor, and with at least some of the processors configured to; route a packet that includes a header and payload from an origin core to a destination core over a route including multiple cores in the multi-core processor device; and at each core in the route before the destination core, route the packet to the next core in the route according to a value of a respective symbol in a sequence of multiple symbols in the header, with the respective symbol having a first symbol value indicating a single likely direction and the respective symbol having a second, different symbol value indicating routing according to at least one of multiple less likely routing directions. - View Dependent Claims (14, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification