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Condensed router headers with low latency output port calculation

  • US 8,572,353 B1
  • Filed: 09/20/2010
  • Issued: 10/29/2013
  • Est. Priority Date: 09/21/2009
  • Status: Active Grant
First Claim
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1. A method for communicating among cores in a multi-core processor device that comprises a plurality of cores, each core comprising a processor and a switch, the method comprising:

  • routing a packet that includes a header and payload from an origin core to a destination core over a route including multiple cores in the multi-core processor device; and

    at each core in the route before the destination core, routing the packet to the next core in the route according to a value of a respective symbol in a sequence of multiple symbols in the header, with the respective symbol having a first symbol value indicating a single likely direction, and the respective symbol having a second, different symbol value indicating routing according to at least one of multiple less likely routing directions.

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