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Method for performing pattern decomposition for a full chip design

  • US 8,572,521 B2
  • Filed: 11/13/2008
  • Issued: 10/29/2013
  • Est. Priority Date: 11/13/2007
  • Status: Active Grant
First Claim
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1. A computer-implemented method for decomposing a target pattern containing features to be printed on a wafer, into multiple patterns, comprising the steps of:

  • segmenting said target pattern into a plurality of patches;

    for each of said plurality of patches, identifying critical features within each patch which violate minimum spacing requirements;

    identifying one or more critical groups in each patch having identified critical features, wherein said critical groups respectively comprise a plurality of features including one or more of said identified critical features;

    generating a critical group graph for each of said plurality of patches having critical features, said critical group graph of a given patch linking together the critical groups and thereby defining a coloring scheme for said critical groups in said given patch, wherein said respective plurality of features within a single critical group share the same color;

    identifying critical groups in said plurality of patches that have features extending into adjacent patches;

    generating a global critical group graph for said target pattern, including stitching together said critical group graphs of each of said plurality of patches, and inserting graph edges between said critical groups that have said features extending into adjacent patches; and

    coloring said features in said target pattern in accordance with said global critical group graph by assigning a color to each of said critical groups,wherein one or more of the steps of segmenting, identifying, generating a critical group graph, generating a global critical group graph and coloring are implemented using a computer.

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