Accurate parasitic capacitance extraction for ultra large scale integrated circuits
First Claim
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1. A method comprising:
- reading a technology file into an extraction system; and
reading a circuit layout into said extraction system;
wherein said technology file includes a capacitance table;
wherein a connector capacitance in said capacitance table is derived from an effective connector area table; and
wherein each element of said effective connector area table is calibrated to have a parasitic capacitance value matching with a measured parasitic capacitance of an actual connector configuration in an integrated circuit (IC), said actual connector configuration including a via, a contact, or a combination thereof.
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Abstract
A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
62 Citations
20 Claims
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1. A method comprising:
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reading a technology file into an extraction system; and reading a circuit layout into said extraction system; wherein said technology file includes a capacitance table; wherein a connector capacitance in said capacitance table is derived from an effective connector area table; and wherein each element of said effective connector area table is calibrated to have a parasitic capacitance value matching with a measured parasitic capacitance of an actual connector configuration in an integrated circuit (IC), said actual connector configuration including a via, a contact, or a combination thereof. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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reading a technology file into an extraction system; reading a circuit layout into said extraction system; processing a geometry of said circuit layout in said extraction system; and using said extraction system, extracting parasitic capacitance by pattern-matching a connector configuration in said technology file to a pattern in said circuit layout; wherein said technology file includes a capacitance table; wherein a connector capacitance in said capacitance table is derived from an effective connector area table; and wherein each element of said effective connector area table is calibrated to have a parasitic capacitance value matching with a measured parasitic capacitance of an actual connector configuration in an integrated circuit (IC), said actual connector configuration including a via, a contact, or a combination thereof. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification