MRAM fabrication method with sidewall cleaning

• US 8,574,928 B2
• Filed: 04/10/2012
• Issued: 11/05/2013
• Est. Priority Date: 04/10/2012
• Status: Active Grant

• Current Assignee: Avalanche Technology Incorporated
• Original Assignee: Avalanche Technology Incorporated
• Inventors: Satoh, Kimihiro, Huai, Yiming, Zhou, Yuchen, Zhang, Jing, Jung, Dong Ha, Abedifard, Ebrahim, Ranjan, Rajiv Yadav, Keshtbod, Parviz
• Primary Examiner(s): ARORA, AJAY
• Application Number:
  US13/443,818
• Publication Number:
  US 20130267042A1
• Time in Patent Office: 574 Days
• Field of Search: 438/3
• US Class Current: 438/3
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

Claims

1. A method for fabricating thin film magnetic memory cells on a wafer comprising:

depositing a stack of layers for a magnetic tunnel junction memory device including a top electrode, a bottom electrode and an upper magnetic layer and a lower magnetic layer separated by a barrier layer;

patterning the stack of layers to form a plurality of pillars with an upper surface being the top electrode and the upper magnetic layer and the barrier layer having exposed sidewalls, the patterning resulting in re-deposition material being deposited on the exposed sidewalls of the upper magnetic layer and the barrier layer;

vertically depositing a layer of a first dielectric material over the pillars including the top electrodes and on the sidewalls of the upper magnetic layers and the barrier layers having re-deposition material deposited thereon;

physically etching the pillars so that the top surface of the pillars is etched faster than other surfaces of the pillar, the etching continuing until the first dielectric material has been removed from the top electrode and first dielectric material along with the re-deposited material has been removed the sidewalls of the upper magnetic layer and the barrier layer;

depositing an oxygen-free second dielectric material over the pillars on the wafer;

depositing an inter-layer dielectric (ILD) material over the pillars on the wafer, the ILD material having a higher etching rate in a first selected dry etching process than the second dielectric material;

planarizing the wafer using chemical-mechanical polishing (CMP);

patterning trench lines across the top electrodes, the patterning including using the first selected dry etching process to remove inter-layer dielectric (ILD) material down to the second dielectric material which acts as an etch stop;

removing second dielectric material to expose the top electrodes in the pillars using a second selected dry etching process; and

depositing metal over the exposed top electrodes in the trench lines.

2. The method of claim 1 wherein physically etching the pillars further comprises dry etching using an inert gas while applying electrical bias to the wafer.

3. The method of claim 1 wherein the second dielectric material is a silicon nitride or a silicon carbide.

4. The method of claim 1 wherein the inter-layer dielectric (ILD) material is silicon oxide.

5. The method of claim 1 wherein physically etching the pillars further comprises isotropically etching surfaces of the pillars other than the top surface.

6. The method of claim 1 physically etching the pillars leaves residual first dielectric material on planar surfaces between the pillars.

7. The method of claim 6 wherein physically etching the pillars leaves residual re-deposition material on the sidewalls of the bottom electrodes.

8. A method for fabricating thin film magnetic memory cells on a wafer comprising:

depositing a stack of layers for a magnetic tunnel junction memory device including a top electrode, a bottom electrode and an upper magnetic layer and a lower magnetic layer separated by a barrier layer;

patterning the stack of layers to form a plurality of pillars with an upper surface being the top electrode and the upper magnetic layer and the barrier layer having exposed sidewalls, the patterning resulting in re-deposition material being deposited on the exposed sidewalls of the upper magnetic layer and the barrier layer;

depositing a layer of oxygen-free first dielectric material over the pillars including the top electrodes and on the sidewalls of the upper magnetic layers and the barrier layers having re-deposition material deposited thereon, the dielectric material being relatively thin on top of the pillars and relatively thicker in the areas between the pillars;

etching the first dielectric material and re-deposition material using a high density plasma CVD process with a chemistry system selected for more rapid removal of the first dielectric material and slower removal of material forming in the top electrode, the etching continuing until the sidewalls of the barrier layers have been cleaned of re-deposition material;

depositing an oxygen-free second dielectric material over the pillars on the wafer;

depositing an inter-layer dielectric (ILD) material over the pillars on the wafer, the ILD material having a higher etching rate in a first selected dry etching process than the oxygen-free second dielectric material;

planarizing the wafer using chemical-mechanical polishing (CMP);

patterning trench lines across the top electrodes, the patterning including using the first selected dry etching process to remove inter-layer dielectric (ILD) material down to the oxygen-free second dielectric material which acts as an etch stop;

removing oxygen-free second dielectric material to expose the top electrodes in the pillars using a second selected dry etching process; and

depositing metal over the exposed top electrodes in the trench lines.

9. The method of claim 8 wherein the oxygen-free second dielectric material is silicon nitride or silicon carbide.

10. The method of claim 8 wherein the a chemistry system in the CVD process is CH₃OH or CO/NH₃.

11. A method for fabricating thin film magnetic memory cells on a wafer comprising:

depositing a stack of layers for a magnetic tunnel junction memory device including a top electrode, a bottom electrode and an upper magnetic layer and a lower magnetic layer separated by a barrier layer;

patterning the stack of layers to form a plurality of pillars with an upper surface being the top electrode and the upper magnetic layer and the barrier layer having exposed sidewalls, the patterning resulting in re-deposition material being deposited on the exposed sidewalls of the upper magnetic layer and the barrier layer;

depositing an oxygen-free first dielectric material over the pillars including the top electrodes and on the sidewalls of the upper magnetic layers and the barrier layers having re-deposition material deposited thereon, the first dielectric material having a thickness that is less than the height of the barrier layer in the pillars;

depositing a second dielectric material to a thickness that is greater than the thickness first dielectric material;

planarizing the wafer using chemical-mechanical polishing (CMP);

vertically etching the first and second dielectric materials using a chemistry system that removes of the first and second dielectric materials more rapidly than the material in the top electrodes, the vertical etching continuing until the first dielectric material and the re-deposition material have been removed from the sidewalls of the barrier layers;

depositing an oxygen-free third dielectric material over the pillars on the wafer;

depositing an inter-layer dielectric (ILD) material over the pillars on the wafer, the ILD material having a higher etching rate in a first selected dry etching process than the oxygen-free third dielectric material;

planarizing the wafer using chemical-mechanical polishing (CMP);

patterning trench lines across the top electrodes, the patterning including using the first selected dry etching process to remove inter-layer dielectric (ILD) material down to the third dielectric material which acts as an etch stop;

removing third dielectric material to expose the top electrodes in the pillars using a second selected dry etching process; and

depositing metal over the exposed top electrodes in the trench lines.

12. The method of claim 11 wherein the chemistry system used in vertically etching the first and second dielectric materials is CH₃OH or CO/NH₃.

13. The method of claim 11 wherein the first dielectric material is selected to be silicon nitride or silicon carbide.

14. The method of claim 11 wherein the second dielectric material is a silicon oxide.