Method to form a 3D semiconductor device and structure

• US 8,574,929 B1
• Filed: 11/16/2012
• Issued: 11/05/2013
• Est. Priority Date: 11/16/2012
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak, Cronquist, Brian
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US13/678,584
• Time in Patent Office: 354 Days
• Field of Search: 257/E21.614
• US Class Current: 438/4
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

A method to form a monolithic 3D device including: processing a first layer including first mono-crystal transistors; transferring a second mono-crystal layer on top of the first layer including first mono-crystal transistors by using ion-cut layer transfer; and repairing the damage caused by the ion-cut by using optical annealing.

Claims

1. A method to form a monolithic 3D device, the method comprising:

processing a first layer comprising first mono-crystal transistors;

transferring a second mono-crystal layer on top of said first layer by using an ion-cut layer transfer; and

repairing damage caused by said ion-cut using optical annealing.

2. The method according to claim 1, comprising forming a heat-spreader layer between said first layer and said second mono-crystal layer.

3. The method according to claim 1, comprising forming a through second mono-crystal layer via,

wherein said through second mono-crystal layer via is part of a heat removal structure of said device.

4. The method according to claim 1, comprising forming a plurality of thermal conducting paths from locations in said second mono-crystal layer to said first layer.

5. The method according to claim 1, comprising forming JFET transistors comprising said second mono-crystal layer, wherein said JFET transistors comprise a doped polysilicon gate.

6. The method according to claim 1, comprising forming gates for second transistors, said second transistors at least partly within said second mono-crystal layer, wherein said forming gates is performed after said repairing.

7. The method according to claim 1, comprising:

forming second transistors, said second transistors at least partly within said second mono-crystal layer; and

forming connections between a plurality of said second transistors,

wherein at least one of said connections is under said second mono-crystal layer, and at least one of said connections is overlying said second mono-crystal layer.

8. A method to form a monolithic 3D device, the method comprising:

processing a first layer comprising first mono-crystal transistors;

wherein an interconnection layer comprising aluminum or copper is formed overlaying said first layer;

transferring a second mono-crystal layer on top of said interconnection layer by using an ion-cut layer transfer; and

repairing damage caused by said ion-cut using optical annealing;

wherein said optical annealing is performed without damaging said interconnection layer; and

wherein second transistors are formed at least partly within said second mono-crystal layer.

9. The method according to claim 8, wherein said second transistors are formed by gate replacement.

10. The method according to claim 8, comprising forming at least one thermally conductive and electrically non-conducting contact to at least one of said second transistors.

11. The method according to claim 8, comprising forming a plurality of thermal conducting paths from locations in said second mono-crystal layer to said first layer.

12. The method according to claim 8, wherein said second transistors are JFET transistors comprising a doped polysilicon gate.

13. The method according to claim 8, comprising forming connections between a plurality of said second transistors,

wherein at least one of said connections is under said second mono-crystal layer, and at least one of said connections is overlying said second mono-crystal layer.

14. The method according to claim 8, comprising forming a mobile system comprising the device formed by the method of claim 8.

15. A method to form a monolithic 3D device, the method comprising:

processing a first layer comprising first mono-crystal transistors;

transferring a second mono-crystal layer on top of said first layer by using an ion-cut layer transfer; and

repairing damage caused by said ion-cut using optical annealing;

wherein second transistors are formed at least partly within said second mono-crystal layer; and

wherein a shielding layer is formed between said first layer and said second mono-crystal layer.

16. The method according to claim 15, wherein said shielding layer is part of a thermal connection path from said second mono-crystal layer to a surface of said device.

17. The method according to claim 15, comprising:

forming a power distribution network to provide power to said second transistors,

wherein said power distribution network provides a heat removal path to at least one of said second transistors.

18. The method according to claim 15, comprising forming a plurality of thermal conducting paths from locations in said second mono-crystal layer to said first layer.

19. The method according to claim 15, wherein said second transistors are JFET transistors comprising a doped polysilicon gate.

20. The method according to claim 15, comprising forming connections between a plurality of said second transistors,

wherein at least one of said connections is under said second mono-crystal layer, and at least one of said connections is overlying said second mono-crystal layer.

21. The method according to claim 15, comprising forming a mobile system comprising the device.

22. The method according to claim 15, wherein said first layer comprises a first alignment mark and wherein said forming second transistors comprises alignment to said first alignment mark.

23. The method according to claim 15, comprising at least one connection through said second mono-crystal layer, wherein said connection comprises material whose coefficient of thermal expansion is within 50% of the coefficient of thermal expansion of said second mono-crystal layer.

24. A method to form a monolithic 3D device, the method comprising:

processing a first layer comprising first mono-crystal transistors;

transferring a second mono-crystal layer on top of said first layer by using an ion-cut layer transfer;

repairing damage caused by said ion-cut using optical annealing;

wherein second vertically oriented transistors are formed at least partly within said second mono-crystal layer.

25. The method according to claim 24, comprising forming at least one shielding layer between said first layer and said second mono-crystal layer.

26. The method according to claim 24, comprising forming a plurality of thermal conducting paths from locations in said second mono-crystal layer to said first layer.

27. The method according to claim 24, wherein said second transistors are JFET transistors comprising a doped polysilicon gate.

28. The method according to claim 24, comprising forming connections between a plurality of said second transistors,

wherein at least one of said connections is under said second mono-crystal layer, and at least one of said connections is overlying said second mono-crystal layer.

29. The method according to claim 24, comprising forming a mobile system comprising the device.

30. The method according to claim 24, comprising at least one connection through said second mono-crystal layer, wherein said connection comprises material whose coefficient of thermal expansion is within 50% of the coefficient of thermal expansion of said second mono-crystal layer.