Semiconductor optoelectronics structure with increased light extraction efficiency and fabrication method thereof

• US 8,574,939 B2
• Filed: 07/14/2010
• Issued: 11/05/2013
• Est. Priority Date: 07/15/2009
• Status: Expired due to Fees

• Current Assignee: Advanced Optoelectronic Technology, Inc.
• Original Assignee: Advanced Optoelectronic Technology, Inc.
• Inventors: Shen, Chia Hui, Huang, Shih Cheng, Tu, Po Min, Wu, Peng Yi, Lin, Wen Yu, Ma, Chih Pang, HONG, TZU CHIEN
• Primary Examiner(s): Mondt, Johannes P
• Application Number:
  US12/836,075
• Publication Number:
  US 20110012155A1
• Time in Patent Office: 1,210 Days
• Field of Search: None
• US Class Current: 438/42
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/10 with a light reflecting structure, e.g. semiconductor Bragg reflector
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/36 characterised by the electrodes

Abstract

A semiconductor optoelectronic structure with increased light extraction efficiency and a fabrication method thereof are presented. The semiconductor optoelectronic structure includes continuous grooves formed under an active layer of the semiconductor optoelectronic structure to reflect light from the active layer and thereby direct more light through a light output surface so as to increase the light intensity from the semiconductor optoelectronic structure.

Claims

1. A method for fabricating a semiconductor optoelectronic device, comprising the steps of:

providing a substrate;

forming a patterned silicon dioxide layer on the substrate;

forming an upper buffer layer on the patterned silicon dioxide layer;

forming a semiconductor layer on the upper buffer layer;

removing the patterned silicon dioxide layer to form a groove pattern layer having a plurality of grooves;

roughening the upper buffer layer from a side of the groove pattern layer;

etching the semiconductor layer to form a cutting region; and

forming a transparent electrically conductive layer on the semiconductor layer.

2. The method of claim 1, wherein the plurality of grooves is formed on the upper buffer layer and adjacent to the substrate.

3. The method of claim 1, further comprising a step of forming a lower buffer layer between the substrate and the patterned silicon dioxide layer.

4. The method of claim 3, wherein the plurality of grooves is formed between the upper buffer layer and the lower buffer layer.

5. The method of claim 1, wherein the patterned silicon dioxide layer is removed using buffered oxide etchant solution.

6. The method of claim 1, wherein the semiconductor layer comprises at least an n-type conductive layer on the upper buffer layer and a p-type conductive layer over the n-type conductive layer, the method further comprising a step of roughening a surface of the p-type conductive layer, performed before the step of forming a transparent electrically conductive layer.

7. The method of claim 1, wherein the semiconductor layer comprises at least an n-type conductive layer on the upper buffer layer and a p-type conductive layer over the n-type conductive layer, the method further comprising a step of forming an insulating layer configured to cover the p-type conductive layer and the n-type conductive layer but to expose a p-type electrode and an n-type electrode.

8. The method of claim 1, wherein the groove pattern layer is partially continuous.

9. The method of claim 1, wherein the groove pattern layer has a height of from 0.05 to 2 micrometers.

10. The method of claim 2, wherein each of the grooves has a width of from 0.1 to 10 micrometers.

11. The method of claim 1, wherein the semiconductor layer comprises at least an n-type conductive layer on the upper buffer layer, an active layer on the n-type conductive layer and a p-type conductive layer over the active layer, and wherein the active layer is separated from the groove pattern layer by a distance of from 3 to 4 micrometers.

12. The method of claim 1, wherein the semiconductor layer comprises at least an n-type conductive layer on the upper buffer layer, an active layer on the n-type conductive layer and a p-type conductive layer over the active layer, and wherein the active layer is separated from a top surface of the p-type conductive layer by a distance of from 0.15 to 0.3 micrometers.

13. The method of claim 1, wherein the step of roughening the upper buffer layer from the side of the groove pattern layer is performed by introducing etchant into the groove pattern layer for etching surfaces of the upper buffer layer over the grooves.