Method of manufacturing semiconductor device having metal gate

• US 8,574,990 B2
• Filed: 02/24/2011
• Issued: 11/05/2013
• Est. Priority Date: 02/24/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Liao, Po-Jui, Tsai, Tsung-Lung, Lin, Chien-Ting, Hsu, Shao-Hua, Lu, Shui-Yen, Chou, Pei-Yu, Liao, Jiunn-Hsiung, Tsai, Shang-Yuan, Yang, Chan-Lon, Tsai, Teng-Chun, Lin, Chun-Hsien, Chen, Shin-Chi
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US13/033,616
• Publication Number:
  US 20120220113A1
• Time in Patent Office: 985 Days
• Field of Search: 438275-278
• US Class Current: 438/275
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.

Claims

1. A method of manufacturing a semiconductor device having metal gate, comprising:

providing a substrate, wherein a first conductive type transistor and a second conductive type transistor are disposed on the substrate, and the first conductive type transistor comprises a first sacrifice gate and the second conductive type transistor comprises a second sacrifice gate;

removing the first sacrifice gate of the first conductive type transistor to form a first trench;

forming a first metal layer and a first material layer in the first trench;

simultaneously planarizing the first metal layer and the first material layer outside the first trench;

after planarizing the first metal layer and the first material layer, removing the second sacrifice gate of the second conductive type transistor to form a second trench without using a mask layer;

forming a second metal layer and a second material layer in the second trench; and

planarizing the second metal layer and the second material layer.

2. The method of manufacturing a semiconductor device having metal gate according to claim 1, wherein the first metal layer comprises TiN or TaC.

3. The method of manufacturing a semiconductor device having metal gate according to claim 1, wherein the second metal layer comprises TiAl, ZrAl, WAl, TaAl or HfAl.

4. The method of manufacturing a semiconductor device having metal gate according to claim 1, wherein the first material layer comprises a spin-on-polymer layer, a bottom anti-reflective coating (BARC) layer, a carbon containing dielectric layer, a sacrificial light absorbing material (SLAM) or a photoresist layer.

5. The method of manufacturing a semiconductor device having metal gate according to claim 4, wherein the second material layer comprises a spin-on-polymer layer, a bottom anti-reflective coating (BARC) layer, a carbon containing dielectric layer, a sacrificial light absorbing material (SLAM) or a photoresist layer.

6. The method of manufacturing a semiconductor device having metal gate according to claim 5, after planarizing the second metal layer and the second material layer, further comprising:

removing the first material layer in the first trench and the second material layer in the second trench;

forming a third conductive layer in the first trench and the second trench; and

planarizing the third conductive layer.

7. The method of manufacturing a semiconductor device having metal gate according to claim 6, wherein the third metal layer comprises Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W, Ti/TiN or carbon nanotube.

8. The method of manufacturing a semiconductor device having metal gate according to claim 1, wherein the first material layer comprises a spin-on-polymer layer, a bottom anti-reflective coating (BARC) layer, a carbon containing dielectric layer, a sacrificial light absorbing material (SLAM) or a photoresist layer.

9. The method of manufacturing a semiconductor device having metal gate according to claim 8, wherein the second material layer comprises Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W, Ti/TiN or carbon nanotube.

10. The method of manufacturing a semiconductor device having metal gate according to claim 9, after planarizing the second metal layer and the second material layer, further comprising:

removing the first material layer in the first trench;

forming a third conductive layer in the first trench; and

planarizing the third conductive layer.

11. The method of manufacturing a semiconductor device having metal gate according to claim 10, wherein the third metal layer comprises Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W, Ti/TiN or carbon nanotube.

12. The method of manufacturing a semiconductor device having metal gate according to claim 1, wherein the first material layer comprises Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W, Ti/TiN or carbon nanotube.

13. The method of manufacturing a semiconductor device having metal gate according to claim 12, wherein the second material layer comprise Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W, Ti/TiN or carbon nanotube.

14. The method of manufacturing a semiconductor device having metal gate according to claim 1, wherein the step of removing the second sacrifice gate of the second conductive type transistor comprises a wet etching step.

15. The method of manufacturing a semiconductor device having metal gate according to claim 1, wherein the step of removing the second sacrifice gate of the second conductive type transistor consist of a wet etching step.

16. The method of manufacturing a semiconductor device having metal gate according to claim 15, wherein the wet etching step comprises using a solution with ozone and 1 to 4% TMAH by volume.

17. The method of manufacturing a semiconductor device having metal gate according to claim 1, wherein the step of removing the first sacrifice gate of the first conductive type transistor comprises:

forming a mask layer;

forming a first patterned photoresist layer to cover the second conductive type transistor; and

removing the first sacrifice gate and the mask layer not covered by the first patterned photoresist layer.

18. The method of manufacturing a semiconductor device having metal gate according to claim 17, further comprising forming an auxiliary layer on the mask layer, wherein the auxiliary layer comprises SiO₂.

19. The method of manufacturing a semiconductor device having metal gate according to claim 17, further comprising:

performing a trimmed process toward the first patterned photoresist layer to form a second patterned photoresist layer, wherein the width of the second patterned photoresist layer is substantially less than that of the first patterned photoresist layer;

removing the portions of the mask layer and the first sacrifice gate not covered by the second patterned photoresist layer;

removing the second patterned photoresist layer; and

performing a wet etching process to completely remove the first sacrifice gate.

20. The method of manufacturing a semiconductor device having metal gate according to claim 19, wherein the trimmed process uses a plasma gas comprising O₂, O₃, CF₄ or HBr.