Lateral trench mosfet having a field plate

• US 8,575,015 B2
• Filed: 08/23/2011
• Issued: 11/05/2013
• Est. Priority Date: 02/06/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Denison, Marie
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): Nicely, Joseph C
• Application Number:
  US13/215,731
• Publication Number:
  US 20110306172A1
• Time in Patent Office: 805 Days
• Field of Search: 438/197, 438/270, 438/272, 438/589, 438/282, 257/396, 257/622, 257/E21.373, 257/E21.452, 257/E21.655, 257/E21.668
• US Class Current: 438/589
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes source and drain regions having a body region therebetween. A gate electrode region is disposed in a trench that extends beneath the surface of the semiconductor body at least partially between the source and drain. A gate dielectric separates the gate electrode region from the semiconductor body. In addition, a field plate region in the trench is coupled to the gate electrode region, and a field plate dielectric separates the field plate region from the semiconductor body. Other integrated circuits and methods are also disclosed.

Claims

1. A method of forming an integrated circuit, comprising:

forming an epitaxial layer of semiconductor material of first conductivity type over a semiconductor substrate;

forming a laterally elongated trench in the epitaxial layer;

forming a layer of dielectric material on sidewalls and a bottom of the trench;

forming a layer of hard mask material over the dielectric layer within the trench;

forming a deep well of the first conductivity type in the epitaxial layer laterally spaced from an end of the trench;

performing a first etch to remove a selected portion of the layer of dielectric material from the sidewalls and bottom at an opposite end of the trench;

forming a shallow well of a second conductivity type to define a body region of a MOSFET within the epitaxial layer, underneath and surrounding sides of a remaining portion of the layer of dielectric material proximate the opposite end;

wherein forming the shallow well includes implanting dopant underneath the remaining portion through a portion of the trench vacated by the removed portion of the layer of dielectric material;

forming a shallow implant region of the first conductivity type to define a source region of the MOSFET underneath and surrounding the opposite end of the trench;

performing a second etch through the portion of the trench vacated by the removed portion of the layer of dielectric material to remove another portion of the first layer of dielectric material from the sidewalls and bottom proximate the opposite end of the trench;

removing the layer of hard mask material from the trench;

forming a gate dielectric layer over the sidewalls and bottom of portions of the vacated by the removed portion and removed another portion of the layer of dielectric material; and

forming a layer of gate electrode material within the trench, to define a gate electrode of the MOSFET over the layer of gate dielectric material and to define a field plate of the MOSFET over remaining portions of the layer of dielectric material.

2. The method of claim 1, further comprising forming a buried layer of the first conductivity type in the semiconductor substrate to define a buried drain region of the MOSFET;

the epitaxial layer being formed over the buried layer, and a bottom surface of the trench being separated from the buried layer.

3. The method of claim 2, wherein the layer of hard mask material comprises polysilicon.

4. The method of claim 3, wherein the first etch is an anisotropic etch, and the second etch is an isotropic etch.

5. The method for claim 4, wherein the isotropic etch is a wet etch that undercuts the layer of hard mask material proximate the opposite end of the trench.

6. The method of claim 5, wherein removing the layer of hard mask material includes performing a third etch.

7. The method of claim 1, wherein the first etch is an anisotropic etch, and the second etch is an isotropic etch.

8. The method for claim 7, wherein the isotropic etch is a wet etch that undercuts the layer of hard mask material proximate the opposite end of the trench.

9. The method of claim 1, wherein removing the layer of hard mask material includes performing a third etch.