Method and apparatus for filling interconnect structures

• US 8,575,028 B2
• Filed: 05/16/2011
• Issued: 11/05/2013
• Est. Priority Date: 04/15/2011
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Inventors: Reid, Jonathan D., Zhu, Huanfeng
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US13/108,894
• Publication Number:
  US 20120264290A1
• Time in Patent Office: 904 Days
• Field of Search: 438/678, 257/E21.591
• US Class Current: 438/687
• CPC Class Codes: C25D 17/001 Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
• CPC Class Codes: C25D 17/008 Current shielding devices
• CPC Class Codes: C25D 21/12 Process control or regulation controlling or regulating in general G05
• CPC Class Codes: C25D 3/38 of copper
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/6723 comprising at least one plating chamber electroless plating apparatuses C23C, electroplating apparatuses C25D
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76882 Reflowing or applying of pressure to better fill the contact hole

Abstract

Methods, apparatus, and systems for depositing copper and other metals are provided. In some implementations, a wafer substrate is provided to an apparatus. The wafer substrate has a surface with field regions and a feature. A copper layer is plated onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the feature. Implementations of the disclosed methods, apparatus, and systems allow for void-free bottom-up fill of features in a wafer substrate.

Claims

1. A method comprising:

(a) providing a wafer substrate to an apparatus, the wafer substrate including a surface with field regions and a feature;

(b) electroplating a copper layer onto the surface of the wafer substrate; and

(c) annealing the copper layer, wherein the annealing reflows the copper in the copper layer and causes redistribution of the copper from the field regions of the wafer substrate to the feature.

2. The method as recited in claim 1, wherein the annealing the copper layer is at a temperature of about 150 to 400°

C.

3. The method as recited in claim 1, wherein the annealing the copper layer is for a duration of about 30 to 180 seconds.

4. The method as recited in claim 1, wherein the annealing the copper layer is performed in a reducing atmosphere.

5. The method as recited in claim 1, wherein the reducing atmosphere is selected from the group consisting of forming gas, atomic hydrogen, and other chemical reducing agents.

6. The method as recited in claim 1, wherein the surface of the wafer includes a liner layer over the field regions and the feature.

7. The method as recited in claim 6, further comprising:

annealing the liner layer in a reducing atmosphere prior to electroplating the copper layer.

8. The method as recited in claim 6, wherein the liner layer is selected from the group consisting of ruthenium (Ru), cobalt (Co), tungsten (W), osmium (Os), platinum (Pt), palladium (Pd), gold (Au), and rhodium (Rh).

9. The method as recited in claim 1, wherein the copper layer includes a copper alloying element.

10. The method as recited in claim 1, wherein a width or diameter of the feature is less than about 100 nanometers.

11. The method as recited in claim 1, wherein the aspect ratio of the feature is less than about 15:

1.

12. The method as recited in claim 1, wherein the copper layer is about 2 to 20 nanometers thick.

13. The method as recited in claim 1, further comprising:

after the annealing redistributes copper from regions of the wafer substrate to the feature such that an aspect ratio of the feature is about 2;

1 or less, electroplating copper onto the copper layer to fill the feature.

14. The method as recited in claim 1, further comprising:

repeating operations (b) and (c) until an aspect ratio of the feature is about 2;

1 or less.

15. The method as recited in claim 1, further comprising:

repeating operations (b) and (c) about 2 to 8 times.

16. The method as recited in claim 1, further comprising:

after annealing the copper layer, electroplating a copper alloy layer onto the copper layer.

17. The method as recited in claim 1, wherein the copper layer is continuous.

18. The method as recited in claim 1, wherein the electroplating is performed at a temperature of about room temperature.

19. The method as recited in claim 1, wherein the electroplating is performed at a temperature of about 50 to 90°

C.

20. The method as recited in claim 1, further comprising:

applying a photoresist to the wafer substrate;

exposing the photoresist to light;

patterning the photoresist and transferring the pattern to the wafer substrate; and

selectively removing the photoresist from the wafer substrate.

22. The method of claim 1, wherein the electroplating is performed in an electroplating solution having a resistivity higher than about 200 ohm-cm.

23. The method of claim 22, wherein the electroplating is performed in an electroplating solution having a resistivity higher than about 1000 ohm-cm.

21. A method comprising:

(a) providing a wafer substrate to an apparatus, the wafer substrate including a surface covered with a liner layer, the surface including field regions and a feature;

(b) plating a copper layer onto the surface of the wafer substrate with an electroplating process; and

(c) annealing the copper layer, wherein the annealing the copper layer is performed in a reducing atmosphere at a temperature of about 150 to 400°

C. for a duration of about 30 to 180 seconds, and wherein the annealing reflows the copper in the copper layer and causes redistribution of the copper from the field regions of the wafer substrate to the feature.

24. The method of claim 21, wherein the plating is performed in an electroplating solution having a resistivity higher than about 200 ohm-cm.

25. The method of claim 24, wherein the plating is performed in an electroplating solution having a resistivity higher than about 1000 ohm-cm.