Image sensor array for back side illumination with global shutter using a junction gate photodiode

• US 8,575,531 B2
• Filed: 08/16/2011
• Issued: 11/05/2013
• Est. Priority Date: 04/26/2011
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Hynecek, Jaroslav, Komori, Hirofumi
• Primary Examiner(s): PYO, KEVIN K
• Application Number:
  US13/210,619
• Publication Number:
  US 20120273654A1
• Time in Patent Office: 812 Days
• Field of Search: 250/208.1, 250/214.1, 257/222, 257/291, 257/292, 257/E31.097, 257/E27.159, 438/76
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14679 Junction field effect transistor [JFET] imagers; static induction transistor [SIT] imagers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

The present invention provides a junction gate photo-diode (JGP) pixel that includes a JGP accumulating charge in response to impinging photons. The JGP is positioned on a substrate and includes a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer. Also includes is a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier. Also includes is a pinned barrier (PB) and a storage gate (SG) positioned on the substrate between the JGP and the FD. The PB temporarily blocks charge transfer between the JGP and the FD, and the SG stores the accumulated charge from the JGP, and transfers the stored charge to the FD for readout.

Claims

1. A junction gate photo-diode (JGP) pixel, comprising:

a JGP accumulating charge in response to impinging photons, the JGP positioned on a substrate including a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer;

a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier;

a pinned barrier (PB) and a storage gate (SG) positioned on the substrate between the JGP and the FD,

wherein the PB temporarily blocks charge transfer between the JGP and the FD, and the SG stores the accumulated charge from the JGP, and transfers the stored charge to the FD for readout.

2. The JGP pixel of claim 1, including

a clearing gate (CG) positioned on the substrate adjacent to the JGP, the CG clearing charge accumulated in the JGP.

3. The JGP pixel of claim 1,

wherein the PB is a p-doped region on the substrate that temporarily blocks the flow of electrons.

4. The JGP pixel of claim 3, including

a plurality of other JGPs positioned on the substrate,

a plurality of other SGs positioned on the substrate adjacent to the respective JGPs, and

a plurality of other PBs positioned on the substrate adjacent to the respective SGs,

the JGPs independently coupled to the FD through the respective SGs.

5. The JGP pixel of claim 4,

a plurality of clearing gates (CGs) positioned on the substrate adjacent to the JGPs, the CGs clearing charge accumulated on the JGPs.

6. The JGP pixel of claim 3,

wherein the FD is coupled to a reset line by a metal oxide semi-conductor (MOS) transfer gate, the MOS transfer gate clearing charge accumulated on the FD.

7. The JGP pixel of claim 1,

wherein a plurality of JGP pixels are positioned on the substrate in an array as a complementary metal oxide semi-conductor (CMOS) imager.

8. A method for controlling a junction gate photo-diode (JGP) pixel, the pixel comprising a JGP, the JGP positioned on a substrate including a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer, a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier, a pinned barrier (PB) and a storage gate (SG) positioned on the substrate between the JGP and the FD, a clearing gate (CG) positioned on the substrate adjacent to the JGP, a reset gate positioned on the substrate and coupled to the FD, and a controller, the method comprising:

applying, by the controller, during a reset period, a reset control voltage to the reset gate to clear charge accumulated in the FD, and a clearing control voltage to the CG to clear charge accumulated in the JGP,

applying, by the controller, during an integration period, an integration control voltage to the JGP to accumulate charge in the JGP, a transfer control voltage to the JGP and another transfer control voltage to the SG to transfer the accumulated charge from the JGP to the SG, and a storage control voltage to the SG to store the transferred charge in the SG, and

applying, by the controller, during a readout period, a readout control voltage to the SG to transfer the charge stored in the SG over the PB and into the FD for pixel readout.

9. The JGP pixel of claim 8,

controlling, by the controller, the reset gate to couple the FD to a reset potential during the reset period, and

controlling, by the controller, the CG to transfer electrons from a charge well of the JGP to the n layer of the JGP.

10. The JGP pixel of claim 8,

controlling, by the controller, the integration control voltage to increase potential of a well of the JGP to accumulate charge in the JGP, and

controlling, by the controller, the readout control voltage to decrease a potential of a well of the SG to block charge from flowing into the SG during integration.

11. The JGP pixel of claim 8,

controlling, by the controller, the transfer control voltage to decrease a potential of a well of the JGP to transfer charge into the SG,

controlling, by the controller, the other transfer control voltage to increase a potential of a well of the SG to receive charge from the JGP,

controlling, by the controller, the storage control voltage to decrease the potential of the well of the SG to store the received charge, and

controlling, by the controller, the readout control voltage to decrease the potential of the well of the SG to transfer charge over the PB and into the FD.

12. The JGP pixel of claim 8, including a plurality of other JGPs positioned on the substrate, a plurality of other SGs positioned on the substrate adjacent to the respective JGPs, a plurality of other PBs positioned on the substrate adjacent to the respective SGs, at least one other CG positioned on the substrate, the CG positioned adjacent to at least one of the JGPs and the at least one other CG positioned adjacent to at least another one of the JGPs, the method comprising:

controlling, by the controller, the reset gate to couple the FD to a reset potential during the reset period, and

controlling, by the controller, the CGs to transfer electrons from charge wells of the JGPs to the n layers of the JGPs.

13. The JGP pixel of claim 8, including a plurality of other JGPs positioned on the substrate, a plurality of other SGs positioned on the substrate adjacent to the respective JGPs, a plurality of other PBs positioned on the substrate adjacent to the respective SGs, at least one other CG positioned on the substrate, the CG positioned adjacent to at least one of the JGPs and the at least one other CG positioned adjacent to at least another one of the JGPs, the method comprising:

controlling, by the controller, the integration control voltage to increase potentials of wells of the JGPs to accumulate charge in the JGPs, and

controlling, by the controller, the readout control voltage to decrease potentials of wells of the SGs to block charge from flowing into the SGs during integration.

14. The JGP pixel of claim 8, including a plurality of other JGPs positioned on the substrate, a plurality of other SGs positioned on the substrate adjacent to the respective JGPs, a plurality of other PBs positioned on the substrate adjacent to the respective SGs, at least one other CG positioned on the substrate, the CG positioned adjacent to at least one of the JGPs and the at least one other CG positioned adjacent to at least another one of the JGPs, the method comprising:

controlling, by the controller, the transfer control voltage to decrease potentials of wells of the JGPs to transfer accumulated charge into the SGs,

controlling, by the controller, the other transfer control voltage to increase potentials of wells of the SGs to receive the accumulated charge from the JGPs,

controlling, by the controller, the storage control voltage to decrease the potentials of the wells of the SGs to store the received charge in the SGs, and

controlling, by the controller, the readout control voltage to decrease the potentials of the wells of the SGs to transfer charge over the PB and into the FD.

15. A method for forming a junction gate photo-diode (JGP) pixel on a substrate, the method comprising:

forming a JGP on a substrate, the JGP including a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer, the JGP accumulating charge in response to impinging photons;

forming a floating diffusion (FD) on the substrate;

forming a pinned barrier (PB) and a storage gate (SG) on the substrate between the JGP and the FD; and

forming pixel wiring on the substrate above the JGP, FD, SG and PB, the pixel wiring coupled to the JGP, FD, SG and PB,

wherein the PB temporarily blocks charge transfer between the JGP and the FD, the SG receives the accumulated charge from the JGP, stores the charge in the SG, and transfers the stored charge to the FD.

16. The JGP pixel of claim 15, including

forming a plurality of other JGPs, a plurality of other SGs, a plurality of other PBs and at least one other CG on the substrate, and

forming a plurality of isolation regions on the substrate,

wherein at least one of the JGPs are separated from a first region of the FD by at least one of the SGs and at least one of the PBs, and

wherein at least another one of the JGPs are separated from a second region of the FD by at least another one of the SGs and at least another one of the PBs, the JGPs are separated from each other by the isolation regions.

17. The JGP pixel of claim 16, including

forming a first clearing gate (CG) on the substrate between two of the JGPs, and

forming a second CG on the substrate between two other JGPs.

18. The JGP pixel of claim 15, including

forming an p-doped barrier on the substrate below the SG, the p-doped barrier blocking electrons from transferring between the substrate and a charge well of the SG.

19. The JGP pixel of claim 18, including

forming a light shield on the substrate below the p-doped barrier, the light shield blocking photons from impinging on the substrate.

20. The JGP pixel of claim 15,

wherein the SG is formed to have a well region for storing charge, and a barrier region for blocking charge from transferring back into the JGP during storage and readout.