Lateral super junction device with high substrate-drain breakdown and built-in avalanche clamp diode

• US 8,575,695 B2
• Filed: 11/30/2009
• Issued: 11/05/2013
• Est. Priority Date: 11/30/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur, Bhalla, Anup, Yilmaz, Hamza, Ma, Wilson, Guan, Lingpeng, Lee, Yeeheng, Chen, John
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US12/592,619
• Publication Number:
  US 20110127606A1
• Time in Patent Office: 1,436 Days
• Field of Search: 257/106, 257/175, 257/199, 257/481, 438/237, 438/328
• US Class Current: 257/341
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 27/0705 comprising components of the field effect type
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.

Claims

1. A semiconductor power device comprising:

a semiconductor substrate comprising a super-junction structure including a plurality of alternating P-doped and N-doped layers extending laterally from a source column to a drain column wherein said trench source column and drain column extend downward in said semiconductor substrate through two opposite sides of said super-junction structure disposed in said semiconductor substrate;

a gate column for applying a voltage thereon to control a current transmitted laterally through said super-junction structure between said source and said drain columns;

wherein the semiconductor substrate is a P substrate and wherein the drain column are N+ columns to form a Zener diode at a junction of said drain column with said P substrate to function as a built-in avalanche clamp diode; and

a buried doped region disposed in said semiconductor substrate below the drain column to increase an effective radius below the drain column for suppressing an electrical field crowding.

2. The semiconductor power device of claim 1 wherein:

the buried doped region is an N-buffer layer disposed below said drain column and extended laterally toward the gate column.

3. The semiconductor power device of claim 2 wherein:

the N-buffer layer disposed below the drain column and extended to and an area laterally between the drain column and the gate column.

4. The semiconductor power device of claim 1 wherein:

the buried doped region is an N-buffer region disposed below and surrounding bottom sidewalls and a bottom wall of the drain column.

5. The semiconductor power device of claim 1 further comprising:

a source graded N-Dopant diffusion region and a drain graded N-Dopant diffusion region surrounding sidewalls of said source and drain columns respectively.

6. The semiconductor power device of claim 1 wherein:

said gate further comprises a P+ column disposed in a gate column connected to said P doped layers of said super junction structure for applying a voltage to control a current transmitted through said super junction structure.

7. The semiconductor power device of claim 6 further comprising:

a graded P diffusion region having a graded P dopant profile diffused from said P+ column of said gate column.

8. The semiconductor power device of claim 1 wherein:

said gate further comprises a P+ column connected to said P doped layers of said super junction structure and connected to the P substrate.

9. The semiconductor power device of claim 1 wherein:

said gate further comprises a trench P+ column connected to said P doped layers of said super junction structure and disposed near said source column outside of an area between said source column and said drain column wherein said source column is segmented to have a gap area for said P+ gate column to apply a voltage to control a current transmitted through said super junction structure.

10. The semiconductor power device of claim 1 further comprising:

a conductive field plate disposed on a top surface of said drain N+ column.

11. The semiconductor power device of claim 1 further comprising:

an active area for disposing said super junction structure extends between said source and drain column; and

a termination area outside said active cell area comprises a P+ termination column extending down to the substrate, the P+ termination column being located between the active area and the semiconductor die edge.

12. The semiconductor power device of claim 6 wherein:

said P+ gate column extends into said P substrate at a greater depth in said semiconductor substrate than said source and drain columns.

13. The semiconductor power device of claim 6 further comprising:

a gate electrode comprising a gate metal layer disposed below a bottom surface of said semiconductor substrate.

14. The semiconductor power device of claim 6 further comprising:

wherein the source, drain and gate columns in the super junction structure form a JFET, the semiconductor power device further comprising

a MOSFET connected in a cascode circuit configuration with said JFET.

15. The semiconductor power device of claim 6 further comprising:

source/gate fingers having source and gate columns staggered along the length of the source/gate finger; and

drain fingers having a drain column running along the length of the drain finger;

wherein

the source/gate are interdigitated with the drain fingers.

16. The semiconductor power device of claim 15 wherein:

the semiconductor surface in the vicinity to the tips of the source/gate and drain fingers are implanted the same conductivity type as the column located at the tips of the fingers.

17. A method for manufacturing a semiconductor power device on a semiconductor substrate comprising:

forming alternating P type and N type layers over a P substrate, the alternating P type and N type layers being charge balanced to function as a lateral super junction structure;

forming a P gate column through said lateral super junction structure reaching the P substrate; and

forming N source and N drain columns in through said lateral super junction structure; and

forming an avalanche clamping diode between the bottom of the N drain column and the P substrate, the avalanche clamping diode diverting avalanche current away from the super junction structure.

18. A method for manufacturing a semiconductor power device on a semiconductor substrate comprising:

forming alternating P type and N type layers over a P substrate, the alternating P type and N type layers being charge balanced to function as a lateral super junction structure;

forming a P gate column through said lateral super junction structure reaching the P substrate; and

forming N source and N drain columns in through said lateral super junction structure; and

forming an N buffer layer under the N drain column to reduce the electric field crowding under the N drain column.