Through-silicon vias for semicondcutor substrate and method of manufacture

• US 8,575,725 B2
• Filed: 03/13/2013
• Issued: 11/05/2013
• Est. Priority Date: 04/13/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chang, Cheng-Hung, Liao, Ebin, Yu, Chia-Lin, Wang, Hsiang-Yi, Chang, Chun Hua, Huang, Li-Hsien, Kuo, Darryl, Wu, Tsang-Jiuh, Chiou, Wen-Chih
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US13/799,760
• Publication Number:
  US 20130193578A1
• Time in Patent Office: 237 Days
• Field of Search: 257/621, 438/667
• US Class Current: 257/621
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 25/043 Stacked arrangements of devices
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0753 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/115 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

Claims

1. A semiconductor component comprising:

a semiconductor substrate having a top surface;

an opening extending from the top surface into the semiconductor substrate, wherein the opening comprises an interior surface;

a first dielectric liner having a first compressive stress disposed on the interior surface of the opening;

a second dielectric liner having a tensile stress disposed on the first dielectric liner;

a third dielectric liner having a second compressive stress disposed on the second dielectric liner;

a metal barrier layer disposed on the third dielectric liner; and

a conductive material disposed on the metal barrier layer and filling the opening.

2. The semiconductor component of claim 1, wherein the first dielectric liner and the third dielectric liner comprise the same dielectric material.

3. The semiconductor component of claim 1, wherein the first dielectric liner and the third dielectric liner comprise different dielectric materials.

4. The semiconductor component of claim 1, wherein the first compressive stress and the second compressive stress are equal.

5. The semiconductor component of claim 1, wherein the first compressive stress and the second compressive stress differ from each other.

6. The semiconductor component of claim 1, wherein at least one of the first compressive stress and the second compressive stress is within a range of 100 MPa to 400 MPa.

7. The semiconductor component of claim 1, wherein the tensile stress is within a range of 50 MPa to 300 MPa.

8. The semiconductor component of claim 1, wherein the first dielectric liner has a first etching rate in a HF solution, the second dielectric liner has a second etching rate in the HF solution, and the first etching rate is less than the second etching rate.

9. The semiconductor component of claim 8, wherein the third dielectric liner has a third etching rate in the HF solution, and the third etching rate is less than the second etching rate.

10. A semiconductor component comprising:

a substrate having a top surface;

an opening extending from the top surface into the substrate, wherein the opening comprises an interior surface;

a first dielectric liner having a first stress disposed on the interior surface of the opening;

a second dielectric liner having a second stress disposed on the first dielectric liner, wherein a direction of the first stress is opposite a direction of the second stress;

a third dielectric liner having a third stress disposed on the second dielectric liner, wherein a direction of the third stress is equal to the direction of the first stress; and

a conductive material disposed on within the third dielectric liner.

11. The semiconductor component of claim 10, wherein the first stress is a compressive stress.

12. The semiconductor component of claim 10, wherein an etch rate of the first dielectric liner in a HF solution is less than an etch rate of the second dielectric liner in the HF solution.

13. The semiconductor component of claim 10, wherein an etch rate of the third dielectric liner in a HF solution is less than an etch rate of the second dielectric liner in the HF solution.

14. The semiconductor component of claim 10, wherein a magnitude of the first stress is different than a magnitude of the third stress.

15. The semiconductor component of claim 10, further comprising a metal barrier layer between the third dielectric liner and the conductive metal, wherein the metal barrier layer comprises a material selected from the group consisting of tantalum, titanium, tantalum nitride and titanium nitride.

16. The semiconductor component of claim 10, wherein the first dielectric liner has a tapered profile, the second dielectric liner has a tapered profile, and the third dielectric liner has a tapered profile.

17. The semiconductor component of claim 10, wherein the first dielectric liner and the third dielectric liner independently comprise a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and phosphosilicate glass (PSG).

18. The semiconductor component of claim 10, wherein the second dielectric liner is conformal with the first dielectric liner, and the third dielectric liner is conformal with the second dielectric liner.

19. A method for forming a semiconductor component comprising:

providing a semiconductor substrate having a top surface;

forming an opening having an interior surface extending from the top surface into the semiconductor substrate, wherein the opening has a top portion and a bottom portion;

depositing a first dielectric liner on the interior surface by a plasma enhanced chemical vapor deposition (PECVD);

depositing a second dielectric liner on the first dielectric liner by a conformal deposition;

depositing a third dielectric liner on the second dielectric liner by a PECVD;

depositing a metal barrier layer on the third dielectric liner; and

filling the remaining opening after the deposition of the three dielectric liners and the metal barrier layer with a conductive material.

20. The method of claim 19, wherein the second dielectric liner has a thickness T3 on the top portion and a thickness T4 on the bottom portion, and a ratio R2 of T3 to T4 is about 1 to about 5.

21. A semiconductor component comprising:

a substrate having a top surface;

an opening extending from the top surface into the substrate, wherein the opening comprises an interior surface;

a first dielectric liner having a first stress disposed over the interior surface of the opening;

a second dielectric liner having a second stress disposed over the first dielectric liner, wherein a direction of the first stress is opposite a direction of the second stress;

a metal barrier disposed over the second dielectric liner; and

a conductive material disposed over the metal barrier.