Semiconductor chip with linear expansion coefficients in direction parallel to sides of hexagonal semiconductor substrate and manufacturing method

• US 8,575,729 B2
• Filed: 05/13/2011
• Issued: 11/05/2013
• Est. Priority Date: 05/18/2010
• Status: Expired due to Fees

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Uchida, Masao, Hayashi, Masashi
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US13/579,432
• Publication Number:
  US 20120319249A1
• Time in Patent Office: 907 Days
• Field of Search: 257/628, 257/E29.003, 257/E21.599, 438/460
• US Class Current: 257/628
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802
• CPC Class Codes: H01L 29/861 Diodes

Abstract

The semiconductor chip (18) of the present invention is a semiconductor chip (18) on which a power semiconductor device (10) is formed, and which includes a semiconductor substrate made from a hexagonal semiconductor, in which the semiconductor substrate has a shape of a rectangle on a principal surface, in which the rectangle is defined by two sides having lengths a and b equal to each other, and in which linear expansion coefficients in directions parallel to the two sides of the semiconductor substrate are equal to each other.

Claims

1. A semiconductor chip on which a power semiconductor device is formed and which comprises a semiconductor substrate made from a hexagonal semiconductor having an anisotropic property in linear expansion coefficient due to a crystal orientation,

wherein the semiconductor substrate has a shape of a rectangle on a principal surface,

wherein the rectangle is defined by two sides having lengths a and b equal to each other,

wherein linear expansion coefficients in directions parallel to the two sides of the semiconductor substrate are equal to each other, and

wherein the principal surface of the semiconductor substrate and a (0001) plane or (000-1) plane of the hexagonal semiconductor form an angle θ

, which satisfies the following expression

−

10°

≦

θ

≦

10°

.

2. A semiconductor chip on which a power semiconductor device is formed and which comprises a semiconductor substrate made from a hexagonal semiconductor,

wherein the semiconductor substrate has a shape of a rectangle on a principal surface,

wherein the rectangle is defined by two sides having lengths a and b equal to each other, and

wherein one of the two sides and a <

11-20>

direction of the hexagonal semiconductor form an angle of 15°

, and another of the two sides and a <

1-100>

direction of the hexagonal semiconductor form an angle of 15°

.

3. The semiconductor chip according to claim 2, wherein the power semiconductor device comprises:

a power semiconductor element formed on the semiconductor substrate; and

a protective film which is provided on the semiconductor substrate so as to cover the power semiconductor element at least partially, and which has an isotropic mechanical property.

4. The semiconductor chip according to claim 3, wherein the power semiconductor element is formed on the principal surface of the semiconductor substrate, and comprises an epitaxial layer made from a same material as the semiconductor substrate.

5. The semiconductor chip according to claim 3, wherein the protective film contains at least one of silicon nitride and silicon oxide.

6. The semiconductor chip according to claim 3, wherein the power semiconductor element comprises a wiring electrode that has an isotropic mechanical property.

7. The semiconductor chip according to claim 6, wherein the wiring electrode is made from aluminum, copper, or an alloy that contains at least one of aluminum and copper.

8. The semiconductor chip according to claim 2, wherein the principal surface of the semiconductor substrate and a (0001) plane or (000-1) plane of the hexagonal semiconductor form an angle θ

, which satisfies the following expression

−

10°

≦

θ

≦

10°

.

9. The semiconductor chip according to claim 2, wherein the semiconductor substrate is a silicon carbide semiconductor substrate.

10. The semiconductor chip according to claim 2, wherein the semiconductor substrate is a gallium nitride semiconductor substrate.

11. The semiconductor chip according to claim 3, wherein the power semiconductor element is one selected from the group consisting of a metal-insulator-semiconductor field effect transistor, a p-n junction diode, and a Schottky barrier diode.

12. The semiconductor chip according to claim 3, wherein the power semiconductor element is a switching element or a rectifier element.

13. A semiconductor wafer, comprising:

a wafer made from a hexagonal semiconductor; and

a plurality of power semiconductor devices formed on the wafer,

wherein the wafer has an anisotropic mechanical property due to crystal orientation on a plane parallel to a principal surface,

wherein the wafer is provided with a mark for determining a crystal direction of the hexagonal semiconductor in at least a part of a circumference of the wafer,

wherein a direction determined by the mark and a <

11-20>

direction or <

1-100>

direction of the hexagonal semiconductor form an angle β

, which satisfies the following Expression (1);

−

5°

≦

β

≦

5°

 

 

(1)

wherein the plurality of power semiconductor devices each has an area defined by a rectangle on the principal surface,

wherein the rectangle is defined by two sides having one side forming an angle γ

with the direction determined by the mark, and the angle γ

satisfies the following Expression (2) or (2′

)

10°

≦

γ

≦

20°

 

 

(2)

40°

≦

γ

≦

50°

 

 

(2′

).

14. The semiconductor wafer according to claim 13, wherein the mark is an orientation flat.

15. The semiconductor wafer according to claim 13, wherein the mark is a notch.

16. A semiconductor wafer, comprising:

a wafer made from a hexagonal semiconductor; and

a plurality of power semiconductor devices formed on the wafer, wherein the wafer has an anisotropic mechanical property due to crystal orientation on a

plane parallel to a principal surface,

wherein the wafer is provided with a mark for determining a crystal direction of the hexagonal semiconductor in at least a part of a circumference of the wafer,

wherein a direction determined by the mark and a <

11-20>

direction or <

1-100>

direction of the hexagonal semiconductor form an angle β

′

, which satisfies a relation

10°

≦

β

′

20°

, and

wherein the plurality of power semiconductor devices each has an area defined by a rectangle on the principal surface of the wafer.

17. A semiconductor chip manufacturing method, comprising the steps of:

dividing a semiconductor wafer, which comprises a wafer made from a hexagonal semiconductor and a plurality of power semiconductor devices formed on the wafer, a plurality of times in parallel to a second direction, which is at an angle of 90°

with a first direction, while moving the semiconductor wafer relative to a dividing position of a wafer dividing device for a distance c at a time in the first direction, which is at an angle of 15°

with a <

11-20>

direction or <

1-100>

direction of the hexagonal semiconductor;

rotating strips of the semiconductor wafer, which are obtained by a division, by 90°

relative to the wafer dividing device; and

dividing the strips of the semiconductor wafer, which are obtained by a division, a plurality of times in parallel to the first direction, while moving the strips of the semiconductor wafer relative to the dividing position of the wafer dividing device for the distance c at a time in the second direction.