Storage element, storage device, and signal processing circuit

• US 8,575,985 B2
• Filed: 12/30/2011
• Issued: 11/05/2013
• Est. Priority Date: 01/05/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohmaru, Takuro, Endo, Masami
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): HUERTA, PABLO S
• Application Number:
  US13/341,412
• Publication Number:
  US 20120170355A1
• Time in Patent Office: 676 Days
• Field of Search: 365/149
• US Class Current: 327/208
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 14/0009 in which the volatile element is a DRAM cell
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/26 including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24 , e.g. alloys
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Claims

1. A storage element comprising:

a first storage circuit;

a second storage circuit comprising;

a first capacitor comprising a pair of first electrodes;

a first transistor comprising a first gate, a first source and a first drain; and

a second transistor comprising a second gate, a second source and a second drain;

a first switch comprising a first terminal and a second terminal;

a second switch comprising a third terminal and a fourth terminal; and

a third switch comprising a fifth terminal and a sixth terminal,

wherein the first storage circuit holds data only in a period during which a power supply voltage is supplied,

wherein the first transistor comprises a channel provided in an oxide semiconductor layer,

wherein one of the first source and the first drain is electrically connected to one of the pair of first electrodes and the second gate,

wherein one of the second source and the second drain is electrically connected to a first power supply line,

wherein the other of the second source and the second drain is electrically connected to the first terminal,

wherein the second terminal is electrically connected to the third terminal,

wherein the fourth terminal is electrically connected to a second power supply line,

wherein a first control signal is input to the first gate,

wherein a conduction state or a non-conduction state in each of the first switch and the second switch is selected by a second control signal which is different from the first control signal,

wherein when one of the first switch and the second switch is in a conduction state, the other of the first switch and the second switch is in a non-conduction state,

wherein a conduction state or a non-conduction state in the third switch is selected by a third control signal which is different from the first control signal and the second control signal,

wherein a signal corresponding to data held in the first storage circuit is input to the other of the first source and the first drain, and

wherein a signal output from the second terminal or an inverted signal of the signal output from the second terminal is input to the first storage circuit through the third switch.

2. The storage element according to claim 1,

wherein the first switch has a conductivity type, and

wherein the second switch has another conductivity type.

3. The storage element according to claim 1, wherein the third switch is an analog switch comprising a transistor.

4. The storage element according to claim 1, wherein the other of the pair of first electrodes is electrically connected to the first power supply line.

5. The storage element according to claim 1, wherein a voltage corresponding to a difference between a potential input to the first power supply line and a potential input to the second power supply line is supplied as the power supply voltage to the first storage circuit.

6. The storage element according to claim 1,

wherein the first transistor comprises the first gate over the oxide semiconductor layer, and a third gate below the oxide semiconductor layer,

wherein the first control signal is input to one of the first gate and the third gate, and

wherein a fourth control signal is input to the other of the first gate and the third gate.

7. A storage device comprising the storage element according to claim 1.

8. A signal processing circuit comprising:

the storage device according to claim 7; and

an arithmetic circuit which transmits data to the storage device and receives data from the storage device.

9. A storage element comprising:

a first storage circuit;

a second storage circuit comprising;

a first capacitor comprising a pair of first electrodes;

a first transistor comprising a first gate, a first source and a first drain;

a second transistor comprising a second gate, a second source and a second drain;

a first switch comprising a first terminal and a second terminal;

a second switch comprising a third terminal and a fourth terminal;

a third switch comprising a fifth terminal and a sixth terminal; and

an inverter,

wherein the first storage circuit holds data only in a period during which a power supply voltage is supplied,

wherein the first transistor comprises a channel provided in an oxide semiconductor layer,

wherein one of the first source and the first drain is electrically connected to one of the pair of first electrodes and the second gate,

wherein one of the second source and the second drain is electrically connected to a first power supply line,

wherein the other of the second source and the second drain is electrically connected to the first terminal,

wherein the second terminal is electrically connected to the third terminal,

wherein the fourth terminal is electrically connected to a second power supply line,

wherein the second terminal, the third terminal, and an input terminal of the inverter are electrically connected to each other,

wherein a first control signal is input to the first gate,

wherein a conduction state or a non-conduction state in each of the first switch and the second switch is selected by a second control signal which is different from the first control signal,

wherein when one of the first switch and the second switch is in a conduction state, the other of the first switch and the second switch is in a non-conduction state,

wherein a conduction state or a non-conduction state in the third switch is selected by a third control signal which is different from the first control signal and the second control signal,

wherein a signal corresponding to data held in the first storage circuit is input to the other of the first source and the first drain, and

wherein a signal output from the inverter or an inverted signal of the signal output from the inverter is input to the first storage circuit through the third switch.

10. The storage element according to claim 9, further comprising a second capacitor comprising a pair of second electrodes,

wherein one of the pair of second electrodes is electrically connected to the input terminal of the inverter, and

wherein the other of the pair of second electrodes is electrically connected to the first power supply line.

11. The storage element according to claim 9,

wherein the first switch has a conductivity type, and

wherein the second switch has another conductivity type.

12. The storage element according to claim 9, wherein the third switch is an analog switch comprising a transistor.

13. The storage element according to claim 9, wherein the other of the pair of first electrodes is electrically connected to the first power supply line.

14. The storage element according to claim 9, wherein a voltage corresponding to a difference between a potential input to the first power supply line and a potential input to the second power supply line is supplied as the power supply voltage to the first storage circuit.

15. The storage element according to claim 9,

wherein the first transistor comprises the first gate over the oxide semiconductor layer, and a third gate below the oxide semiconductor layer,

wherein the first control signal is input to one of the first gate and the third gate, and

wherein a fourth control signal is input to the other of the first gate and the third gate.

16. A storage device comprising the storage element according to claim 9.

17. A signal processing circuit comprising:

the storage device according to claim 16; and

an arithmetic circuit which transmits data to the storage device and receives data from the storage device.

18. A semiconductor device comprising:

a first transistor;

a second transistor, wherein a gate of the first transistor is electrically connected to a gate of the second transistor, a first terminal of the first transistor is electrically connected to a first terminal of the second transistor, and a second terminal of the first transistor is electrically connected to a first voltage source;

a third transistor, wherein a first terminal of the third transistor is electrically connected to a second terminal of the second transistor, and a second terminal of the third transistor is electrically connected to a second voltage source;

a fourth transistor comprising a channel region, the channel region comprising an oxide semiconductor material, wherein a first terminal of the fourth transistor is electrically connected to a gate of the third transistor; and

a first capacitor including a first electrode and a second electrode, wherein the first electrode of the first capacitor is electrically connected to the gate of the third transistor and the first terminal of the fourth transistor, and the second electrode of the first capacitor is electrically connected to the second voltage source.

19. The semiconductor device according to claim 18, further comprising a second capacitor including a first electrode and a second electrode, wherein the first electrode of the second capacitor is electrically connected to the second voltage source, and the second electrode of the second capacitor is electrically connected to the first terminals of the first transistor and the second transistor.

20. The semiconductor device according to claim 19, further comprising an inverter electrically connected to the second electrode of the second capacitor.