Level shift circuit

• US 8,575,987 B2
• Filed: 08/23/2012
• Issued: 11/05/2013
• Est. Priority Date: 01/25/2010
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kikuchi, Kazutaka
• Primary Examiner(s): JAGER, RYAN C
• Application Number:
  US13/593,010
• Publication Number:
  US 20120313686A1
• Time in Patent Office: 439 Days
• Field of Search: 327/333, 326/80, 326/81, 326/68
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.

Claims

1. A level shift circuit comprising:

a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential;

a latch circuit that operates on a power supply of a second potential which is higher than the first potential, the latch circuit having one end thereof connected to an output end of the CMOS inverter circuit and outputting from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal;

a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit, and functions to limit the power supply when the input pulse signal assumes at least a ground level; and

an initialization circuit that allows the one end of the latch circuit to be short-circuited to the power supply of the second potential by an initialization signal,

wherein the power supply circuit comprises a reverse current blocking circuit, the reverse current blocking circuit comprises a blocking MOS transistor inserted between a power supply side of the CMOS inverter circuit and the power supply supplied to the CMOS inverter circuit, a gate of the blocking MOS transistor is coupled to the output pulse signal.

2. The level shift circuit according to claim 1, wherein

the initialization circuit comprises an initializing MOS transistor with a source thereof connected to the power supply of the second potential and a drain thereof connected to the one end of the latch circuit, the initialization signal being supplied to a gate of the initializing MOS transistor, the initializing MOS transistor having a same conductivity type as a MOS transistor that is present on the power supply side of the CMOS inverter circuit.

3. The level shift circuit according to claim 1, wherein

the reverse current blocking circuit operates to block current from flowing from a power supply terminal of the CMOS inverter circuit to the power supply side of the CMOS inverter circuit when the input pulse signal assumes the ground level.

4. The level shift circuit according to claim 1, wherein the initialization signal is a power-on reset signal.

5. The level shift circuit according to claim 1, further comprising:

a blocking inverter circuit with an input end connected to the output pulse signal and an output end connected to the gate of the blocking MOS transistor.

6. The level shift circuit according to claim 1, wherein

the latch circuit comprises an output stage inverter circuit having an input end at the one end of the latch circuit connected to the output end of the CMOS inverter circuit and an output end at the other end of the latch circuit.

7. The level shift circuit according to claim 1, wherein

the initialization signal is generated by an input from a common power-on reset circuit.

8. A level shift circuit comprising:

a CMOS inverter circuit that receives an input signal having a first voltage swing;

a latch circuit that outputs an output signal having a second voltage swing which is larger than the first voltage swing based on a voltage level of an output node of the CMOS inverter circuit;

a power supply circuit that is connected between a first power supply and a power supply terminal of the CMOS inverter circuit, and supplies a first power supply to the CMOS inverter circuit in response to the output signal, a potential of the first power supply is lower than a high-level voltage of the second voltage swing; and

an initialization circuit that supplies a predetermined voltage level to the output node of the CMOS inverter circuit in response to an initialization signal.

9. A level shift circuit comprising:

a CMOS inverter circuit that receives an input signal having a first voltage swing;

a latch circuit that outputs an output signal having a second voltage swing which is larger than the first voltage swing based on a voltage level of an output node of the CMOS inverter circuit;

a power supply circuit that supplies a power supply to the CMOS inverter circuit based on a voltage level of the output signal,

and an initialization circuit that supplies a predetermined voltage level to the output node of the CMOS inverter circuit in response to an initialization signal,

wherein the power supply circuit comprises a reverse current blocking circuit, the reverse current blocking circuit comprises a blocking MOS transistor inserted between a power supply side of the CMOS inverter circuit and the power supply supplied to the CMOS inverter circuit, a gate of the blocking MOS transistor is coupled to the output signal.

10. The level shift circuit according to claim 9, wherein the predetermined voltage level is same as a high-level voltage of the second voltage swing.

11. The level shift circuit according to claim 9, further comprising:

a blocking inverter circuit with an input end connected to the output signal and an output end connected to the gate of the blocking MOS transistor.