3D chip stack skew reduction with resonant clock and inductive coupling

• US 8,576,000 B2
• Filed: 08/25/2011
• Issued: 11/05/2013
• Est. Priority Date: 08/25/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Kim, Jae-Joon, Lin, Yu-Shiang, Pang, Liang-Teck, Silberman, Joel A.
• Primary Examiner(s): LUU, AN T
• Application Number:
  US13/217,349
• Publication Number:
  US 20130049824A1
• Time in Patent Office: 803 Days
• Field of Search: 257/665, 257/676, 257/686, 257691-693, 257/E23.141, 257/E23.144, 257/E23.145, 327564-565
• US Class Current: 327/565
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.

Claims

1. A method for synchronizing global clock signals in a clock distribution network in a 3D chip stack having two or more strata, the method comprising:

arranging each of a plurality of clock distribution circuits on a respective one of the two or more strata to provide the global clock signals to various chip locations;

configuring a respective resonant circuit included in each of the plurality of clock distribution circuits to provide stratum-to-stratum coupling for the clock distribution network, the resonant circuit including at least one capacitor and at least one inductor.

2. The method of claim 1, wherein said configuring step comprises aligning inductor coils included within the resonant circuit on at least two of the two or more strata with respect to each other to form a coupling there between to reduce skewing of the global clock signals with respect to the various chip locations.

3. The method of claim 2, wherein the two or more strata are configured with a front-to-back configuration or a back-to-back configuration, the inductor coils that are aligned to form the coupling are located on respective front-sides of the two or more strata, and the method comprises enhancing the coupling by adding a back-side inductor having inductor coils aligned with the inductor coils on the front-sides.

4. The method of claim 3, wherein the back-side inductor is formed by a re-distribution layer.

5. A method for synchronizing global clock signals in a clock distribution network in a 3D chip stack having two or more strata, the method comprising:

arranging each of a plurality of clock grids on a respective one of the two or more strata to provide the global clock signals to various chip locations;

arranging each of a plurality of buffered clock trees on the respective one of the two or more strata to drive a respective one of the plurality of clock grids on a same one of the two or more strata, each of the plurality of buffered clock trees having at least a root and a plurality of clock buffers;

arranging each of a plurality of multiplexers on the respective one of the two or more strata, the plurality of multiplexers being configured to provide a same single clock source to the root of each of the plurality of buffered clock trees; and

configuring a resonant circuit included in each of the plurality of clock grids to provide stratum-to-stratum coupling for the clock distribution network.