Thin film transistor array substrate for liquid crystal display

• US 8,576,346 B2
• Filed: 03/15/2013
• Issued: 11/05/2013
• Est. Priority Date: 05/16/2001
• Status: Expired due to Fees

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Dung-Gyu
• Primary Examiner(s): DUDEK, JAMES A
• Application Number:
  US13/842,111
• Publication Number:
  US 20130229590A1
• Time in Patent Office: 235 Days
• Field of Search: 349/39, 349/43, 349/44, 349/54, 349/55
• US Class Current: 349/39
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G02F 1/136268 Switch defects
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

A thin film transistor array panel which includes a substrate; a first gate line disposed on the substrate; a second gate line disposed adjacent to the first gate line; a gate insulating layer disposed on the first gate line and the second gate line; a semiconductor pattern disposed on the gate insulating layer and overlapping with the first gate line; a data line crossing the first gate line and the second gate line; a thin film transistor connected to the second gate line and the data line; and a floating electrode disposed on the semiconductor pattern, wherein the floating electrode is disposed at a same layer as the data line.

Claims

1. A thin film transistor array panel comprising:

a substrate;

a first gate line disposed on the substrate;

a second gate line disposed adjacent to the first gate line;

a gate insulating layer disposed on the first gate line and the second gate line;

a semiconductor pattern disposed on the gate insulating layer and overlapping the first gate line;

a data line crossing the first gate line and the second gate line;

a thin film transistor connected to the second gate line and the data line; and

a floating electrode disposed on the semiconductor pattern,

wherein the floating electrode is disposed at a same layer as the data line.

2. The thin film transistor array panel of claim 1, further comprising a pixel electrode connected to the thin film transistor.

3. The thin film transistor array panel of claim 2, wherein a portion of the pixel electrode overlaps the first gate line.

4. The thin film transistor array panel of claim 3, further comprising a storage capacitance wire disposed between the first gate line and the second gate line, and overlapping an edge of the pixel electrode,

wherein the storage capacitance wire has a first electrode line extending parallel to the second gate line, and a second electrode line connected to the first electrode line and extending parallel to the data line.

5. The thin film transistor array panel of claim 4, wherein the second electrode line is disposed along the edge of the pixel electrode.

6. The thin film transistor array panel of claim 5, wherein the second electrode line comprises a right electrode line and a left electrode line,

wherein the right electrode line and the left electrode line are at least partially positioned over the pixel electrode.

7. The thin film transistor array panel of claim 5, wherein the first electrode line fully overlaps the pixel electrode.

8. The thin film transistor array panel of claim 6, wherein the second electrode line overlaps at least one edge of the pixel electrode.

9. The thin film transistor array panel of claim 7, wherein the second electrode line overlaps two opposing edges of the pixel electrode.

10. The thin film transistor array panel of claim 1, wherein a semiconductor pattern of the thin film transistor lies within edges of the second gate line.

11. The thin film transistor array panel of claim 1, wherein the second gate line is electrically connected to the thin film transistors of an (n)th row of the array, and the first gate line is electrically connected to the thin film transistors of an (n−

1)th row of the array.

12. A liquid crystal display device comprising:

a first substrate comprising a common electrode; and

a second substrate opposing the first substrate with a liquid crystal layer therebetween, the second substrate comprising;

a first gate line disposed on the second substrate;

a second gate line disposed proximate to the first gate line;

a gate insulating layer disposed on the first gate line and the second gate line;

a semiconductor pattern disposed on the gate insulating layer and overlapping the first gate line;

a data line crossing the first gate line and the second gate line;

a thin film transistor connected to the second gate line and the data line; and

a floating electrode disposed on the semiconductor pattern;

wherein the floating electrode is disposed at a same layer as the data line, and

wherein the device displays a white color when no voltage is applied to the pixel electrode.

13. The thin film transistor array panel of claim 12, further comprising a pixel electrode connected to the thin film transistor.

14. The thin film transistor array panel of claim 13, wherein a portion of the pixel electrode overlaps the first gate line.

15. The thin film transistor array panel of claim 14, further comprising a storage capacitance wire disposed between the first gate line and the second gate line, and overlapping an edge of the pixel electrode,

wherein the storage capacitance wire has a first electrode line extending parallel to the second gate line, and a second electrode line connected to the first electrode line and extending parallel to the data line.

16. The thin film transistor array panel of claim 15, wherein the second electrode line is disposed along the edge of the pixel electrode.

17. The liquid crystal display device of claim 16, wherein the first electrode line fully overlaps the pixel electrode.

18. The liquid crystal display device of claim 17, wherein the second electrode line overlaps at least one edge of the pixel electrode.

19. The liquid crystal display device of claim 18, wherein the second electrode line overlaps two opposing edges of the pixel electrode.

20. The liquid crystal display device of claim 12, wherein a semiconductor pattern of the thin film transistor lies within edges of the second gate line.