Multi-wafer 3D CAM cell

• US 8,576,599 B2
• Filed: 02/02/2012
• Issued: 11/05/2013
• Est. Priority Date: 05/18/2007
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Atwal, Jagreet S., Barnes, Joseph S., Bernstein, Kerry, Bucki, Robert J., Cox, Jason A.
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US13/364,607
• Publication Number:
  US 20120127771A1
• Time in Patent Office: 642 Days
• Field of Search: 365/49.1, 365/49.11, 365/49.17
• US Class Current: 365/49.1
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.

Claims

1. A method of operating a multi-operational-mode multi-wafer device configured for operation in a first mode as a CAM cell and for operation in a second mode as a register, said method comprising:

providing a multi-operational-mode multi-wafer device comprising first semiconductor components and second semiconductor components, wherein said first semiconductor components are configured as a match circuitry and comprise at least one compare element and a first power distribution structure comprising first power wires located in a first dielectric material layer, and wherein said second semiconductor components are configured as a storage circuitry vertically stacked on top of, or below, said first semiconductor components, said second semiconductor components comprising at least one storage element and a second power distribution structure comprising second power wires located in a second-dielectric material layer, wherein said second power distribution structure overlies or underlies said first power distribution structure, and said first semiconductor components and said second semiconductor components are interconnected by at least one vertically conductive filled via hole, and said first power distribution structure does not contact said second power distribution structure;

operating a combination of said first semiconductor components and said second semiconductor components as said CAM cell in a first mode, wherein said first power distribution structure provides a first non-zero power supply voltage to said first semiconductor components during operation in said first mode; and

operating said second semiconductor components as a register in a second mode, wherein said first power distribution structure turns off said match circuitry during operation in said second mode, and wherein said second power distribution structure provides a second non-zero power supply voltage to said second semiconductor components.

2. The method of claim 1, wherein said at least one compare element is located above said at least one storage element within said multi-operational-mode multi-wafer device.

3. The method of claim 1, wherein said at least one compare element comprises a plurality of first transistors that have a 9T configuration and said at least one storage element comprises a plurality of second transistors having a 6T configuration.

4. The method of claim 3, wherein said plurality of first transistors are located upon and within a top, active semiconductor layer of a first semiconductor-on-insulator substrate, and said plurality of said second transistors are located upon and within a top, active semiconductor layer of a second semiconductor-on-insulator substrate.

5. The method of claim 4, wherein said first and second semiconductor-on-insulator substrates each include a buried insulating layer directly beneath the top, active semiconductor layer.

6. The method of claim 1, wherein said at least one vertically conductive filled via hole is located within at least one dielectric material that is present within one of said first and second dielectric material layers.

7. The method of claim 1, wherein said first semiconductor components are embedded in a dielectric material that is present within one of said first and second dielectric material layers, and has conductive filled openings that are in contact with surfaces of at least one first transistor, and said second semiconductor components are embedded in another dielectric material that is present within another of said first and second dielectric material layers, and has conductive filled openings that are in contact with surfaces of at least one second transistor.