Semiconductor device and driving method thereof

• US 8,576,620 B2
• Filed: 11/12/2010
• Issued: 11/05/2013
• Est. Priority Date: 11/13/2009
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): RADKE, JAY W
• Application Number:
  US12/945,476
• Publication Number:
  US 20110116310A1
• Time in Patent Office: 1,089 Days
• Field of Search: 365/182
• US Class Current: 365/182
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.

Claims

1. A semiconductor device comprising:

a source line;

a bit line;

a word line;

a first signal line;

a second signal line;

a memory cell connected to the source line, the bit line, the word line, the first signal line, and the second signal line;

a driver circuit configured to drive the second signal line and the word line so as to select the memory cell specified by an address signal;

a writing circuit configured to output a writing potential to the first signal line;

a reading circuit configured to compare a potential of the bit line with a plurality of reading potentials;

a control circuit configured to select one of a plurality of voltages for correction on a basis of comparison results between the potential of the bit line and the plurality of reading potentials; and

a potential generating circuit configured to generate the writing potential and the plurality of reading potentials to supply to the writing circuit and the reading circuit.

2. A semiconductor device comprising:

a source line;

a bit line;

a word line;

a first signal line;

a second signal line;

a memory cell connected to the source line, the bit line, the word line, the first signal line, and the second signal line;

a driver circuit configured to drive the second signal line and the word line so as to select the memory cell specified by an address signal;

a writing circuit configured to output a first writing potential to the first signal line in a first writing operation and outputs one of a plurality of second writing potentials to the first signal line in a second writing operation;

a reading circuit configured to compare a first potential of the bit line with a plurality of first reading potentials in a first reading operation and compare a second potential of the bit line with a plurality of second reading potentials in a second reading operation to read out data of the memory cell;

a control circuit configured to select one of a plurality of voltages for correction on a basis of comparison results between the first potential of the bit line and the plurality of first reading potentials and select one of the plurality of second writing potentials; and

a potential generating circuit configured to generate the first writing potential, the plurality of second writing potentials, the plurality of first reading potentials, and the plurality of second reading potentials to supply to the writing circuit and the reading circuit.

3. A semiconductor device comprising:

a source line;

a bit line;

a first signal line;

a plurality of second signal lines;

a plurality of word lines;

a plurality of memory cells connected in parallel between the source line and the bit line;

a driver circuit configured to drive the plurality of second signal lines and the plurality of word lines so as to select the memory cell specified by an address signal;

a writing circuit configured to output a writing potential to the first signal line;

a reading circuit configured to compare a potential of the bit line with a plurality of reading potentials;

a control circuit configured to select one of a plurality of voltages for correction on a basis of comparison results between the potential of the bit line and the plurality of reading potentials; and

a potential generating circuit configured to generate the writing potential and the plurality of reading potentials to supply to the writing circuit and the reading circuit,

wherein one of the plurality of memory cells includes;

a first transistor which includes a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor which includes a second gate electrode, a second source electrode, and a second drain electrode; and

a third transistor which includes a third gate electrode, a third source electrode, and a third drain electrode,

wherein the first transistor is provided in a substrate containing a semiconductor material,

wherein the second transistor includes a semiconductor layer containing an In—

Ga—

Zn—

O-based semiconductor material,

wherein the first gate electrode is electrically connected to one of the second source electrode or the second drain electrode,

wherein the source line is electrically connected to the first source electrode,

wherein the first drain electrode is electrically connected to the third source electrode,

wherein the bit line is electrically connected to the third drain electrode,

wherein the first signal line is electrically connected to the other of the second source electrode or the second drain electrode,

wherein one of the plurality of the second signal lines is electrically connected to the second gate electrode, and

wherein one of the plurality of word lines is electrically connected to the third gate electrode.

4. The semiconductor device according to claim 3, wherein the first transistor includes a channel region provided in the substrate containing the semiconductor material, impurity regions provided so as to sandwich the channel region, a first gate insulating layer over the channel region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode electrically connected to the impurity regions.

5. The semiconductor device according to claim 3, wherein the second transistor includes the second gate electrode over the substrate containing the semiconductor material, a second gate insulating layer over the second gate electrode, the semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode which are electrically connected to the semiconductor layer.

6. The semiconductor device according to claim 3, wherein the substrate containing the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

7. The semiconductor device according to claim 3, wherein the semiconductor material is silicon.

8. The semiconductor device according to claim 3, wherein the semiconductor layer is an oxide semiconductor layer.

9. The semiconductor device according to claim 3, wherein the semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

10. The semiconductor device according to claim 8, wherein a hydrogen concentration of the oxide semiconductor layer is 5×

10¹⁹ atoms/cm³ or less.

11. The semiconductor device according to claim 3, wherein an off-state current of the second transistor is 1×

10<sup>−

13</sup> A or less.

12. A semiconductor device comprising:

a source line;

a bit line;

a first signal line;

a plurality of second signal lines;

a plurality of word lines;

a plurality of memory cells connected in parallel between the source line and the bit line;

a driver circuit configured to drive the plurality of second signal lines and the plurality of word lines so as to select the memory cell specified by an address signal;

a writing circuit configured to output a first writing potential to the first signal line in a first writing operation and outputs one of a plurality of second writing potentials to the first signal line in a second writing operation;

a reading circuit configured to compare a first potential of the bit line with a plurality of first reading potentials in a first reading operation and compare a second potential of the bit line with a plurality of second reading potentials in a second reading operation to read out data of the memory cell;

a control circuit configured to select one of a plurality of voltages for correction on a basis of comparison results between the first potential of the bit line and the plurality of first reading potentials and select one of the plurality of second writing potentials; and

a potential generating circuit configured to generate the first writing potential, the plurality of second writing potentials, the plurality of first reading potentials, and the plurality of second reading potentials to supply to the writing circuit and the reading circuit,

wherein one of the plurality of memory cells includes;

a first transistor which includes a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor which includes a second gate electrode, a second source electrode, and a second drain electrode; and

a third transistor which includes a third gate electrode, a third source electrode, and a third drain electrode,

wherein the first transistor is provided in a substrate containing a semiconductor material,

wherein the second transistor includes a semiconductor layer containing an In—

Ga—

Zn—

O-based semiconductor material,

wherein the first gate electrode is electrically connected to one of the second source electrode or the second drain electrode,

wherein the source line is electrically connected to the first source electrode,

wherein the first drain electrode is electrically connected to the third source electrode,

wherein the bit line is electrically connected to the third drain electrode,

wherein the first signal line is electrically connected to the other of the second source electrode or the second drain electrode,

wherein one of the plurality of the second signal lines is electrically connected to the second gate electrode, and

wherein one of the plurality of word lines is electrically connected to the third gate electrode.

13. The semiconductor device according to claim 12, wherein the first transistor includes a channel region provided in the substrate containing the semiconductor material, impurity regions provided so as to sandwich the channel region, a first gate insulating layer over the channel region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode electrically connected to the impurity regions.

14. The semiconductor device according to claim 12, wherein the second transistor includes the second gate electrode over the substrate containing the semiconductor material, a second gate insulating layer over the second gate electrode, the semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode which are electrically connected to the semiconductor layer.

15. The semiconductor device according to claim 12, wherein the substrate containing the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

16. The semiconductor device according to claim 12, wherein the semiconductor material is silicon.

17. The semiconductor device according to claim 12, wherein the semiconductor layer is an oxide semiconductor layer.

18. The semiconductor device according to claim 12, wherein the semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

19. The semiconductor device according to claim 17, wherein a hydrogen concentration of the oxide semiconductor layer is 5×

10¹⁹ atoms/cm³ or less.

20. The semiconductor device according to claim 12, wherein an off-state current of the second transistor is 1×

10<sup>−

13</sup> A or less.

21. A method for driving a semiconductor device comprising:

a source line;

a bit line;

a word line;

a first signal line;

a second signal line;

a driver circuit configured to drive the second signal line and the word line so as to select a memory cell specified by an address signal;

a writing circuit;

a reading circuit;

a control circuit;

a potential generating circuit; and

the memory cell connected to the source line, the bit line, the word line, the first signal line, and the second signal line, the method for driving the semiconductor device comprising;

outputting a writing potential to the first signal line connected to the specified memory cell from the writing circuit in a first writing operation;

in a first reading operation, comparing a first potential of the bit line with a plurality of first reading potentials in the reading circuit and selecting one of a plurality of voltages for correction on a basis of comparison results thereof in the control circuit; and

outputting a writing potential which is corrected on a basis of the voltage for correction to the first signal line connected to the specified memory cell in a second writing operation.

22. A method for driving a semiconductor device comprising:

a source line;

a bit line;

a word line;

a first signal line;

a second signal line;

a driver circuit configured to drive the second signal line and the word line so as to select a memory cell specified by an address signal;

a writing circuit;

a reading circuit;

a control circuit;

a potential generating circuit; and

the memory cell connected to the source line, the bit line, the word line, the first signal line, and the second signal line,

the method for driving the semiconductor device comprising;

outputting a writing potential to the first signal line connected to the specified memory cell from the writing circuit in a first writing operation;

in a first reading operation, comparing a first potential of the bit line with a plurality of first reading potentials in the reading circuit and selecting one of a plurality of voltages for correction on a basis of comparison results thereof in the control circuit;

outputting a writing potential which is corrected on a basis of the voltage for correction to the first signal line connected to the specified memory cell in a second writing operation; and

comparing a second potential of the bit line with a plurality of second reading potentials in the reading circuit to read out data of the memory cell in a second reading operation.