Memory module including memory buffer and memory system having the same

• US 8,576,637 B2
• Filed: 12/03/2010
• Issued: 11/05/2013
• Est. Priority Date: 01/15/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jang, Soon-Deok, Kim, Seok-Il, Seo, Seung-Jin, Han, You-Keun
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): HUERTA, PABLO S
• Application Number:
  US12/959,504
• Publication Number:
  US 20110176371A1
• Time in Patent Office: 1,068 Days
• Field of Search: 365/189.05
• US Class Current: 365/189.05
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits

Abstract

A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal.

Claims

1. A memory buffer, comprising:

a control circuit configured to generate a mode control signal based on a first chip selecting signal and a second chip selecting signal received simultaneously, and a row address strobe signal, a column address strobe signal, and a write enable signal received simultaneously; and

a mode selecting circuit configured to select one of a parallel test mode and a mode register control mode in response to the mode control signal.

2. The memory buffer of claim 1, wherein the memory buffer is configured to enter the parallel test mode when the first chip selecting signal and the second chip selecting signal are enabled, and the row address strobe signal, the column address strobe signal, or the write enable signal is enabled.

3. The memory buffer of claim 2, wherein output signals of the memory buffer corresponding to the first chip selecting signal and the second chip selecting signal are configured to be enabled in the parallel test mode.

4. The memory buffer of claim 1, wherein the memory buffer is configured to enter the mode register control mode when the first chip selecting signal and the second chip selecting signal are enabled, and the row address strobe signal, the column address strobe signal, and the write enable signal are disabled.

5. The memory buffer of claim 4, wherein output signals of the memory buffer corresponding to the first chip selecting signal and the second chip selecting signal are configured to be disabled in the mode register control mode.

6. The memory buffer of claim 1, wherein the memory buffer is configured to enter the parallel test mode when the first chip selecting signal and the second chip selecting signal are enabled, and output signals of the memory buffer corresponding to the first chip selecting signal and the second chip selecting signal are enabled.

7. The memory buffer of claim 1, wherein the memory buffer is configured to enter the mode register control mode when the first chip selecting signal and the second chip selecting signal are enabled, and output signals of the memory buffer corresponding to the first chip selecting signal and the second chip selecting signal are disabled.

8. The memory buffer of claim 1, wherein the control circuit includes:

a NOR gate for performing a logical NOR operation with respect to the first chip selecting signal and the second chip selecting signal;

a NAND gate for performing a logical NAND operation with respect to the row address strobe signal, the column address strobe signal, and the write enable signal; and

an AND gate for performing a logical AND operation with respect to an output signal of the NOR gate, and an output signal of the NAND gate to generate the mode control signal.

9. A memory module, comprising:

a substrate;

a plurality of semiconductor memory devices, each mounted on a surface of the substrate and configured to operate in response to a command and an address signal and a data signal; and

a memory buffer configured to select a mode from modes including a parallel test mode and a mode register control mode based at least on a first chip selecting signal and a second chip selecting signal received simultaneously.

10. The memory module of claim 9, wherein the memory buffer includes:

a circuit configured to select one of the parallel test mode and the mode register control mode based on the first chip selecting signal, the second chip selecting signal, the row address signal, the column address signal, and the write enable signal.

11. The memory module of claim 10, wherein:

the memory buffer is configured to enter the parallel test mode when the first chip selecting signal and the second chip selecting signal are enabled, and the row address strobe signal, the column address strobe signal, or the write enable signal is enabled; and

the memory buffer is configured to enter the mode register control mode when the first chip selecting signal and the second chip selecting signal are enabled, and the row address strobe signal, the column address strobe signal, and the write enable signal are disabled.

12. The memory module of claim 10, wherein the circuit further comprises:

a NOR gate for performing a logical NOR operation with respect to the first chip selecting signal and the second chip selecting signal;

a NAND gate for performing a logical NAND operation with respect to the row address strobe signal, the column address strobe signal, and the write enable signal; and

an AND gate for performing a logical AND operation with respect to an output signal of the NOR gate, and an output signal of the NAND gate.

13. A memory module comprising:

a substrate;

a plurality of semiconductor memory devices, each mounted on a surface of the substrate and configured to operate in response to a command and an address signal and a data signal;

a memory buffer configured to select a mode from modes including a parallel test mode and a mode register control mode based at least on a first chip selecting signal and a second chip selecting signal;

wherein the memory buffer includes;

a circuit configured to select one of the parallel test mode and the mode register control mode based on the first chip selecting signal, the second chip selecting signal, the row address signal, the column address signal, and the write enable signal;

wherein;

the memory buffer is configured to enter the parallel test mode when the first chip selecting signal and the second chip selecting signal are enabled, and the row address strobe signal, the column address strobe signal, or the write enable signal is enabled; and

the memory buffer is configured to enter the mode register control mode when the first chip selecting signal and the second chip selecting signal are enabled, and the row address strobe signal, the column address strobe signal, and the write enable signal are disabled; and

a plurality of ranks which are tested simultaneously in the parallel test mode.

14. A memory system, comprising:

a memory controller configured to generate a first chip selecting signal, a second chip selecting signal, a row address strobe signal, a column address strobe signal and a write enable signal;

a memory buffer configured to generate a mode control signal based on the first chip selecting signal, the second chip selecting signal, the row address strobe signal, the column address strobe signal, and the write enable signal, and to select a mode from modes including a parallel test mode and a mode register control mode in response to the mode control signal; and

a memory module including semiconductor memory devices that operate in response to the parallel test mode and the mode register control mode,

wherein the memory buffer is configured to enter the parallel test mode when the first chip selecting signal and the second chip selecting signal are enabled, and the row address strobe signal, the column address strobe signal, or the write enable signal is enabled.

15. The memory system of claim 14, wherein the memory buffer is configured to enter the mode register control mode when the first chip selecting signal and the second chip selecting signal are enabled, and the row address strobe signal, the column address strobe signal, and the write enable signal are disabled.

16. A method of setting a mode of a memory module, comprising:

simultaneously inputting a first chip selecting signal, a second chip selecting signal, a row address strobe signal, a column address strobe signal, and a write enable signal to a logic circuit;

outputting one or more output signals from the logic circuit, based on the first chip selecting signal, the second chip selecting signal, the row address strobe signal, the column address strobe signal, and the write enable signal; and

selecting between a parallel test mode and a mode register control mode in response to the one or more output signals.

17. The method of claim 16, wherein the generating of the one or more output signals includes outputting a mode control signal generated by:

performing a logical NOR operation with respect to the first chip selecting signal and the second chip selecting signal to generate a first output signal;

performing a logical NAND operation with respect to the row address strobe signal, the column address strobe signal, and the write enable signal to generate a second output signal; and

performing a logical AND operation with respect to the first output signal and the second output signal to generate the mode control signal.

18. The method of claim 16, further comprising entering the parallel test mode when the first chip selecting signal and the second chip selecting signal are enabled, and the row address strobe signal, the column address strobe signal, or the write enable signal is enabled.

19. The method of claim 16, further comprising entering the mode register control mode when the first chip selecting signal and the second chip selecting signal are enabled, and the row address strobe signal, the column address strobe signal, and the write enable signal are disabled.