Temperature compensation of conductive bridge memory arrays
First Claim
1. A method for operating a non-volatile semiconductor memory array, comprising:
- acquiring a temperature associated with the semiconductor memory array, the semiconductor memory array comprises a cross-point memory array and includes a first set of control lines arranged in a first direction and a second set of control lines arranged in a second direction, the first set of control lines includes a first particular control line and a plurality of other first control lines, the second set of control lines includes a second particular control line and a plurality of other second control lines, the semiconductor memory array includes a first semiconductor storage element disposed between the first particular control line and the second particular control line;
applying a selected first control line voltage to the first particular control line;
applying a selected second control line voltage to the second particular control line;
applying one or more unselected first control line voltages based on the temperature to the plurality of other first control lines;
applying one or more unselected second control line voltages based on the temperature to the plurality of other second control lines; and
setting the first semiconductor storage element into a first state in response to the applying a selected first control line voltage and the applying a selected second control line voltage.
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Accused Products
Abstract
Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.
47 Citations
35 Claims
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1. A method for operating a non-volatile semiconductor memory array, comprising:
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acquiring a temperature associated with the semiconductor memory array, the semiconductor memory array comprises a cross-point memory array and includes a first set of control lines arranged in a first direction and a second set of control lines arranged in a second direction, the first set of control lines includes a first particular control line and a plurality of other first control lines, the second set of control lines includes a second particular control line and a plurality of other second control lines, the semiconductor memory array includes a first semiconductor storage element disposed between the first particular control line and the second particular control line; applying a selected first control line voltage to the first particular control line; applying a selected second control line voltage to the second particular control line; applying one or more unselected first control line voltages based on the temperature to the plurality of other first control lines; applying one or more unselected second control line voltages based on the temperature to the plurality of other second control lines; and setting the first semiconductor storage element into a first state in response to the applying a selected first control line voltage and the applying a selected second control line voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method for operating a non-volatile semiconductor memory array, comprising:
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detecting a first condition associated with the semiconductor memory array, the semiconductor memory array comprises a cross-point memory array, the detecting a first condition includes at least one of detecting a particular temperature associated with the semiconductor memory array or detecting a particular number of write cycles associated with the semiconductor memory array, the semiconductor memory array includes a plurality of word lines arranged in a first direction and a plurality of bit lines arranged in a second direction, the plurality of word lines includes a first word line and one or more other word lines, the plurality of bit lines includes a first bit line and one or more other bit lines, the semiconductor memory array includes a first semiconductor storage element disposed between the first word line and the first bit line; applying a selected word line voltage to the first word line; applying one or more intermediate voltages based on the first condition to the one or more other word lines and the one or more other bit lines; and setting the first semiconductor storage element into a first state in response to the applying a selected word line voltage. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A non-volatile storage system, comprising:
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a semiconductor memory array, the semiconductor memory array comprises a cross-point memory array and includes a plurality of word lines arranged in a first direction and a plurality of bit lines arranged in a second direction, the plurality of word lines includes a first word line and one or more other word lines, the plurality of bit lines includes a first bit line and one or more other bit lines, the semiconductor memory array includes a first semiconductor storage element disposed between the first word line and the first bit line; a first voltage reference circuit, the first voltage reference circuit generates one or more intermediate voltages based on a temperature associated with the semiconductor memory array; a second voltage reference circuit, the second voltage reference circuit generates a selected word line voltage based on the temperature; and one or more managing circuits in communication with the plurality of word lines and the plurality of bit lines, the one or more managing circuits bias the one or more other word lines to the one or more intermediate voltages and bias the one or more other bit lines to the one or more intermediate voltages, the one or more managing circuits bias the first word line to the selected word line voltage and bias the first bit line to a selected bit line voltage. - View Dependent Claims (32, 33, 34, 35)
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Specification