Method and system for slicing a communication signal

• US 8,576,939 B2
• Filed: 10/14/2009
• Issued: 11/05/2013
• Est. Priority Date: 12/22/2003
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Quellan, Inc. (Renesas Electronics Corporation)
• Inventors: Kim, Andrew Joo, Pelard, Cattalen, Gebara, Edward
• Primary Examiner(s): Yu, Lihong
• Application Number:
  US12/578,869
• Publication Number:
  US 20100027709A1
• Time in Patent Office: 1,483 Days
• Field of Search: 375/287
• US Class Current: 375/287
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03312 Arrangements specific to the provision of output signals

Abstract

A slicer can receive a communication signal having a level or amplitude that is between two discrete levels of a multilevel digital communication scheme. The slicer can compare the communication signal to a plurality of references such that multiple comparisons proceed essentially in parallel. A summation node can add the results of the comparisons to provide an output signal set to one of the discrete levels. The slicer can process the communication signal and provide the output signal on a symbol-by-symbol basis. A decision feedback equalizer (“DFE”) can comprise the slicer. A feedback circuit of the DFE can delay and scale the output signal and apply the delayed and scaled signal to the communication signal to reduce intersymbol interference (“ISI”).

Claims

1. A method for processing a communication signal comprising a first signal segment that represents a first symbol and that immediately precedes a second signal segment representing a second symbol, the method comprising:

processing the first signal segment with a front end of a flash converter that comprises a plurality of comparators connected to a corresponding plurality of references, each comparator producing a respective output signal,

wherein the flash converter comprises the front end coupled to a logic circuit and is modified to form a slicer by replacing the logic circuit with a summation node;

setting a signal to a discrete intensity in response to performing a signal summation of the respective output signals with the summation node;

delaying and scaling the signal; and

applying the delayed and scaled signal to the second signal segment to correct interference on the second signal segment,

wherein the front end of the flash converter coupled to the summation node form the slicer having a propagation delay that is less than or equal to a symbol period of the communication signal.

2. The method of claim 1, wherein applying the delayed and scaled signal to the second signal segment comprises correcting intersymbol interference.

3. The method of claim 1, wherein applying the delayed and scaled signal to the second signal segment comprises correcting interference that the first signal segment has imposed on the second signal segment.

4. The method of claim 1, wherein the communication signal further comprises a third signal segment that follows the second signal segment, and

wherein the method further comprises the steps of:

processing the second signal segment with the plurality of comparators, each comparator producing a respective second output signal;

generating a second signal in response to summing the respective second output signals;

delaying and scaling the second signal; and

applying the delayed and scaled second signal to the third signal segment to correct interference on the third signal segment.

5. The method of claim 1, wherein a multilevel communication scheme applies consistently to the first signal segment and the second signal segment.

6. The method of claim 1, wherein the plurality of comparators comprises three comparators.

7. The method of claim 1, wherein the first signal segment occupies a first symbol period, and wherein the second signal segment occupies a second symbol period.

8. The method of claim 1, wherein the first signal segment comprises an amplitude that deviates substantially from every level of a multilevel communication scheme that applies to the first signal segment and that applies to the second signal segment.

9. A method for processing a communication signal, comprising:

comparing, using a front end of a flash converter that comprises a plurality of comparators, a first symbol of the communication signal with a plurality of reference voltages, each comparator producing a respective output signal,

wherein the flash converter comprises the front end coupled to a logic circuit, and

wherein the flash converter is modified to form a slicer by substituting the logic circuit of the flash converter with a summation node;

feeding the respective outputs into the summation node that performs a signal summation of the respective output signals to generate a signal comprising a sum of discrete values of a multilevel signaling scheme;

delaying and scaling the signal in a plurality of feedback loops; and

applying the delayed and scaled signal to a second symbol of the communication signal to correct intersymbol interference on the second symbol.

10. The method of claim 9, wherein applying the delayed and scaled signal to the second symbol comprises correcting interference that the first symbol has imposed on the second symbol.

11. The method of claim 9, wherein the communication signal further comprises a third symbol that follows the second symbol, and

wherein the method further comprises the steps of:

comparing, by the plurality of comparators, the second symbol with the plurality of reference voltages, each comparator producing a respective second output signal;

summing the respective second output signals to generate a second signal comprising a sum of discrete values of the multilevel signaling scheme;

delaying and scaling the second signal in the plurality of feedback loops; and

applying the delayed and scaled second signal to the third symbol to correct interference on the third symbol.

12. The method of claim 9, wherein the multilevel signaling scheme applies consistently to the first and second symbols.

13. The method of claim 9, wherein the plurality of comparators comprises three comparators.

14. The method of claim 9, further comprising scaling the respective output signals of the plurality of comparators before the summing to prevent signal saturation at the summation node.

15. The method of claim 9, wherein delaying and scaling the signal comprises respectively delaying and scaling the signal in each of the plurality of feedback loops.

16. The method of claim 9, further comprising setting an amount of scaling, respectively, for each of the plurality of feedback loops.

17. A method for processing a communication signal having a plurality of symbols, comprising:

during a time period less than or equal to a symbol period of the plurality of symbols, comparing, by a plurality of comparators that are arranged as a front end of a flash converter, a symbol of the communication signal with a plurality of reference voltages, each comparator producing a respective output signal having a respective amplitude, and summing the respective amplitudes at a summation node coupled to the plurality of comparators arranged as the front end to generate a signal comprising a sum of discrete values of a multilevel signaling scheme,

wherein the flash converter comprises the front end coupled to a logic circuit, and

wherein the flash converter is adapted to form a slicer by substituting the logic circuit of the flash converter with the summation node;

delaying and scaling the signal in a plurality of feedback loops; and

applying the delayed and scaled signal to a second symbol of the communication signal to correct intersymbol interference on the second symbol.

18. The method of claim 17, wherein applying the delayed and scaled signal to the second symbol comprises correcting interference that the first symbol has imposed on the second symbol.

19. The method of claim 17, wherein the communication signal further comprises a third symbol that follows the second symbol, and

wherein the method further comprises the steps of:

comparing, by the plurality of comparators, the second symbol with the plurality of reference voltages, each comparator producing a respective second output;

summing the respective second outputs to generate a second signal comprising a sum of discrete values of the multilevel signaling scheme;

delaying and scaling the second signal in the plurality of feedback loops; and

applying the delayed and scaled second signal to the third symbol to correct interference on the third symbol.

20. The method of claim 17, further comprising scaling the respective amplitudes of the plurality of comparators before the summing to prevent signal saturation.

21. The method of claim 17, wherein delaying and scaling the signal comprises respectively delaying and scaling the signal in each of the plurality of feedback loops.

22. The method of claim 17, further comprising setting an amount of scaling, respectively, for each of the plurality of feedback loops.