Pulse signal output circuit and shift register
First Claim
1. A pulse signal output circuit comprising:
- a first transistor and a second transistor, a first terminal of the first transistor and a first terminal of the second transistor being electrically connected to a first output terminal;
a third transistor and a fourth transistor, a first terminal of the third transistor and a first terminal of the fourth transistor being electrically connected to a second output terminal;
a fifth transistor; and
a sixth transistor,wherein a first terminal of the fifth transistor, a gate of the first transistor and a gate of the third transistor are electrically connected to each other;
wherein a gate of the fifth transistor, a first terminal of the sixth transistor, a gate of the second transistor and a gate of the fourth transistor are electrically connected to each other; and
wherein a channel of the sixth transistor is longer than a channel of the fourth transistor.
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Accused Products
Abstract
An object of the present invention is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. In an embodiment of the pulse signal output circuit, a transistor has a source terminal or a drain terminal connected to a gate electrode of another transistor having a source terminal or a drain terminal forming an output terminal of the pulse signal output circuit, the channel length of the transistor being longer than the channel length of the other transistor. Thereby, the amount of a leakage current modifying the gate potential of the other transistor can be reduced, and a malfunction of the pulse signal output circuit can be prevented.
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Citations
34 Claims
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1. A pulse signal output circuit comprising:
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a first transistor and a second transistor, a first terminal of the first transistor and a first terminal of the second transistor being electrically connected to a first output terminal; a third transistor and a fourth transistor, a first terminal of the third transistor and a first terminal of the fourth transistor being electrically connected to a second output terminal; a fifth transistor; and a sixth transistor, wherein a first terminal of the fifth transistor, a gate of the first transistor and a gate of the third transistor are electrically connected to each other; wherein a gate of the fifth transistor, a first terminal of the sixth transistor, a gate of the second transistor and a gate of the fourth transistor are electrically connected to each other; and wherein a channel of the sixth transistor is longer than a channel of the fourth transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system-on-panel comprising:
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a substrate; a pixel portion on the substrate; a counter-substrate and a sealant configured to seal the pixel portion between the substrate and the counter-substrate; a driver circuit configured to drive the pixel portion and comprising a shift register; a flexible printed circuit configured to supply the driver circuit with signals and potentials, wherein the shift register comprises a pulse signal output circuit, the pulse signal output circuit comprising; a first transistor and a second transistor, a first terminal of the first transistor and a first terminal of the second transistor being electrically connected to a first output terminal; a third transistor and a fourth transistor, a first terminal of the third transistor and a first terminal of the fourth transistor being electrically connected to a second output terminal; a fifth transistor; and a sixth transistor, wherein a first terminal of the fifth transistor, a gate of the first transistor and a gate of the third transistor are electrically connected to each other; wherein a gate of the fifth transistor, a first terminal of the sixth transistor, a gate of the second transistor and a gate of the fourth transistor are electrically connected to each other; and wherein a channel of the sixth transistor is longer than a channel of the fourth transistor. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A pulse signal output circuit comprising:
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a first transistor and a second transistor, a first terminal of the first transistor and a first terminal of the second transistor being electrically connected to a first output terminal; a third transistor and a fourth transistor, a first terminal of the third transistor and a first terminal of the fourth transistor being electrically connected to a second output terminal; a fifth transistor and a sixth transistor; and a seventh transistor, an eighth transistor and a ninth transistor, wherein a first terminal of the fifth transistor, a first terminal of the sixth transistor, a gate of the first transistor and a gate of the third transistor are electrically connected to each other; wherein a gate of the sixth transistor, a first terminal of the seventh transistor, a first terminal of the eighth transistor, a first terminal of the ninth transistor, a gate of the second transistor and a gate of the fourth transistor are electrically connected to each other; wherein a second terminal of the fifth transistor, a second terminal of the eighth transistor and a second terminal of the seventh transistor are electrically connected to each other; and wherein a channel of the ninth transistor is longer than a channel of the fourth transistor. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27. A system-on-panel comprising:
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a substrate; a pixel portion on the substrate; a counter-substrate and a sealant configured to seal the pixel portion between the substrate and the counter-substrate; a driver circuit configured to drive the pixel portion and comprising a shift register; and a flexible printed circuit configured to supply the driver circuit with signals and potentials, wherein the shift register comprises a pulse signal output circuit, the pulse signal output circuit comprising; a first transistor and a second transistor, a first terminal of the first transistor and a first terminal of the second transistor being electrically connected to a first output terminal; a third transistor and a fourth transistor, a first terminal of the third transistor and a first terminal of the fourth transistor being electrically connected to a second output terminal; a fifth transistor and a sixth transistor; and a seventh transistor, an eighth transistor and a ninth transistor, wherein a first terminal of the fifth transistor, a first terminal of the sixth transistor, a gate of the first transistor and a gate of the third transistor are electrically connected to each other; wherein a gate of the sixth transistor, a first terminal of the seventh transistor, a first terminal of the eighth transistor, a first terminal of the ninth transistor, a gate of the second transistor and a gate of the fourth transistor are electrically connected to each other; wherein a second terminal of the fifth transistor, a second terminal of the eighth transistor and a second terminal of the seventh transistor are electrically connected to each other; and wherein a channel of the ninth transistor is longer than a channel of the fourth transistor. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34)
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Specification