Arrangement comprising an integrated circuit

• US 8,577,031 B2
• Filed: 03/10/2005
• Issued: 11/05/2013
• Est. Priority Date: 03/24/2004
• Status: Active Grant

• Current Assignee: Continental Automotive GmbH (Continental AG)
• Original Assignee: Continental Automotive GmbH (Continental AG)
• Inventors: Asperger, Karl, Kiemes, Jochen, Lange, Roland, Lindinger, Andreas, Rombach, Gerhard
• Primary Examiner(s): Arani, Taghi
• Assistant Examiner(s): LEE, JASON T
• Application Number:
  US10/599,230
• Publication Number:
  US 20080219441A1
• Time in Patent Office: 3,162 Days
• Field of Search: 380/46, 326/8, 257/315, 257/679, 257/922, 257/681
• US Class Current: 380/46
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 2221/2101 Auditing as a secondary aspect

Abstract

An integrated circuit (1) is provided with function modules (2) which comprise a central processing unit (4) for treating data and executing a program and a cache memory (5). Until now, it was complicated and costly to ensure the manipulation security of the modules. The function modules (2) comprise an encoding unit (6) for data encoding and decoding.

Claims

1. An integrated circuit comprising function modules, wherein the function modules comprise:

a central processing unit designed to process data and to execute programs,

a cache memory,

a random-number generator configured to generate at least one cryptological key, and

a first memory storing the at least one cryptological key generated by the random-number generator,

an encryption unit designed to encrypt and decrypt data using the at least one cryptographic key stored in the first memory,

a security sensor system including a protective layer on the integrated circuit including at least one elongated electrical line extending along the surface of the integrated circuit, the security sensor system operable to;

monitor an ohmic resistance of at least one electrical line of the protective layer on the integrated circuit,

compare the monitored ohmic resistance of the at least one electrical line with a resistance limit value,

detect a breaking of the electrical line based on the comparison, and

when a breaking of the electrical line is detected, automatically initiate the deletion of data from at least one memory of the integrated circuit; and

an integrated voltage regulator that regulates an operating voltage or current of the integrated circuit to render the operating voltage or current noisy, thus preventing attacks based on examination of the current of the integrated circuit.

2. The integrated circuit according to claim 1, wherein function modules comprise a real-time clock.

3. The integrated circuit according to claim 1, wherein operating parameters to be monitored additionally is the clock frequency of the real-time clock and/or an operating temperature at a point in the integrated circuit and/or an operating voltage of the integrated circuit.

4. The integrated circuit according to claim 1, wherein the integrated circuit is arranged in a package and has terminal contacts brought out of the package.

5. The integrated circuit according to claim 1, wherein individual function modules have an essentially planar extent and are arranged adjacently to one another in the area of the normal to the surface.

6. The integrated circuit according to claim 1, wherein the function modules comprise an integrated voltage regulator which regulates an operating voltage.

7. The integrated circuit according to claim 1, wherein it is constructed as semiconductor chip.

8. The integrated circuit according to claim 7, wherein semiconductor structures of the individual function modules are intermeshed in the manner of a puzzle in order to avoid individual function modules from being recognizable.

9. The integrated circuit according to claim 7, wherein an active protective layer which consists of at least one elongated electrical line which extends along the surface of a die of the semiconductor chip, particularly in mutually parallel tracks section by section, is applied directly to the die of the semiconductor chip.

10. An arrangement comprising an integrated circuit as claimed claim 1, wherein the integrated circuit is connected by means of a data bus to a second memory in which data are stored encrypted, wherein the second memory has memory cells which in each case have a memory address and each memory cell can be addressed directly in reading or writing manner.

11. The arrangement according to claim 10, wherein the second memory is volatile and is connected to a battery so that the voltage supply is maintained when another power supply is lacking.

12. The arrangement according to claim 10, wherein the integrated circuit is connected by means of a data bus to a non-volatile third memory in which data or program code are stored encrypted.

13. The arrangement according to claim 10, wherein the security sensor system is connected to a battery so that the voltage supply is maintained if another power supply is lacking.

14. The arrangement according to claim 10, wherein the security sensor system is connected to an auxiliary power source, integrated in the package, which provides the power for deleting the first memory.

15. The arrangement according to claim 12, wherein the third memory is a Flash memory or ROM.

16. An integrated circuit comprising function modules, wherein the function modules comprise:

a central processing unit designed to process data and to execute programs,

a cache memory,

an encryption unit designed to encrypt and decrypt data and the function modules comprise a security sensor system including a protective layer on the integrated circuit including at least one elongated electrical line extending along the surface of the integrated circuit, the security sensor system operable to monitor the state of the protective layer on the integrated circuit such that when a breaking of the electrical line is detected, data is automatically deleted from at least one memory of the integrated circuit,

a random-number generator and a first memory in which cryptological keys are stored, and wherein cryptological keys which are stored in the first memory are generated by means of the random-number generator, and

an integrated voltage regulator that regulates an operating voltage or current of the integrated circuit to render the operating voltage or current noisy, thus preventing attacks based on examination of the current of the integrated circuit.

17. An integrated circuit system including:

an integrated circuit comprising;

a central processing unit designed to process data and to execute programs,

a first memory storing a cryptographic key,

an encryption unit designed to encrypt and decrypt data using the cryptographic key stored in the first memory,

a security sensor system including a protective encapsulation of the integrated circuit and a monitoring system that monitors the state of the protective encapsulation of the integrated circuit such that when a destroyed state of the protective layer is detected, data is automatically deleted from at least one memory of the integrated circuit, and

at least one terminal contact extending through the protective encapsulation of the integrated circuit, and

an external second memory located physically outside the protective encapsulation of the integrated circuit and connected to the integrated circuit via the at least one terminal contact extending through the protective encapsulation of the integrated circuit, and connected to the encryption unit of the integrated circuit via a data bus extending through the at least one terminal contact, the external second memory storing data encrypted with the cryptographic key stored in the first memory,

wherein the encryption unit is designed to read data or code out of the external second memory, decrypt the data or code using the cryptographic key stored in the first memory, and write the decrypted data or code into the first memory or other memory of the integrated circuit.