Rapidly deployed modular telemetry system

• US 8,577,519 B1
• Filed: 03/20/2012
• Issued: 11/05/2013
• Est. Priority Date: 03/20/2012
• Status: Active Grant

• Current Assignee: The United States Of America As Represented By The National Aeronautics And Space Administration
• Original Assignee: United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration
• Inventors: Sims, William Herbert III, Varnavas, Kosta A.
• Primary Examiner(s): Cheung, Mary
• Assistant Examiner(s): BRUSHABER, FREDERICK M
• Application Number:
  US13/424,898
• Time in Patent Office: 595 Days
• Field of Search: 701/3, 342/352
• US Class Current: 701/3
• CPC Class Codes: H04B 7/18519 Operations control, administration or maintenance

Abstract

The present invention is a telemetry system, and more specifically is a rapidly deployed modular telemetry apparatus which utilizes of SDR technology and the FPGA programming capability to reduce the number of hardware components and programming required to deploy a telemetry system.

Claims

1. A rapidly deployed modular telemetry system comprised of:

at least one flight computer;

at least one microcontroller;

at least one FPGA component configured with CCSDS compliant software, said FPGA being operatively connected with said at least one microcontroller;

at least one error-checking encoder component operatively connected with said microprocessor to perform at least one error-checking protocol;

at least one flight computer interface operatively connected with said at least one FPGA and said at least one flight computer;

at least one receiver deck;

at least one transmitter deck; and

at least one power source.

2. The telemetry system of claim 1 wherein said at least one error-checking encoder is configured with software to perform the Reed-Solomon protocol to create at least one telemetry data signal.

3. The telemetry system of claim 2 wherein said at least one error-checking encoder configured with software to perform the Reed-Solomon protocol is structurally integrated with said at least one FPGA.

4. The telemetry system of claim 1 wherein said at least one FPGA is configured with software to perform the BCH error checking protocol to create at least one telemetry data signal.

5. The telemetry system of claim 1 wherein said at least one FPGA is configured with software to perform the pseudo randomization protocol to create at least one telemetry data signal.

6. The telemetry system of claim 1 wherein said at least one error-checking encoder is structurally integrated with said at least one FPGA to perform at least one CCSDS complaint error-checking protocol.

7. The telemetry system of claim 1 wherein said FPGA is configured with software to perform CCSDS protocols selected from the group consisting of Turbo codes, convolutional code, Viterbi, encryption, auto-ranging, low density parity check, other versions of the BCH error-correcting protocol and combinations thereof.

8. The telemetry system of claim 1 wherein said at least one microcontroller is a PIC M32.

9. The telemetry system of claim 1 wherein said flight computer interface is a synchronous 422 interface.

10. The telemetry system of claim 1 wherein said flight computer interface is a universal asynchronous receiver/transmitter (UART) interface.

11. The telemetry system of claim 1 wherein said at least one power source is at least 200 mW.

12. The telemetry system of claim 1 further including a check module operatively connected between said at least one FPGA and said at least one microcontroller.

13. The telemetry system of claim 1 wherein said at least one FPGA performs telemetry uplink processing with uplink processing components consisting of filters, synchronizers, error-checking and general packet processing components that can interface to said at least one flight computer.

14. The telemetry system of claim 1 wherein said at least one FPGA performs telemetry uplink processing with uplink processing components selected from the group consisting of bit syncs, randomizers, BCH encoders, BCH processors, FIFO control processes, FIFO computer chips and combinations thereof.

15. The telemetry system of claim 1 wherein said FPGA performs telemetry downlink processing with downlink processing components consisting of forward error-correction and additional packet processing software components that can interface to said at least one flight computer.

16. The telemetry system of claim 1 wherein said FPGA performs telemetry downlink processing with downlink processing components selected from the group consisting of sync marker generator, Reed-Solomon ASIC control, pseudo random generator, multiplexer and combinations thereof.

17. A telemetry system for a micro satellite comprised of:

at least one transmitter which transmits at least one telemetry signal to at least one flight computer interface;

at least one interchangeable FEC error checking encoder comprised of a single FPGA into which an FEC error checking protocol has been embedded;

at least one receiver; and

at least one power source,

wherein all other processing, error checking, modulation and demodulation are performed on said single FPGA.

18. The telemetry system of claim 17 wherein said FEC error checking protocol is a Reed-Solomon error checking protocol.

19. The telemetry system of claim 17 wherein said FPGA is further configured to perform convolutional encoding.

20. The telemetry system of claim 17 wherein said FPGA is a 32-bit ARM processor.

21. The telemetry system of claim 17 wherein said at least one interchangeable FEC error checking encoder is configured with CCSDS-compliant software.

22. The telemetry system of claim 17 further including at least one microchip operatively connected to said FPGA and said flight computer interface.

23. The telemetry system of claim 22 wherein said at least one microchip is a PIC M32 commercial chip.

24. The telemetry system of claim 17 wherein said at least one interchangeable FEC error checking encoder is configured with software to perform the Reed-Solomon error checking protocol to create at least one telemetry data signal.

25. The telemetry system of claim 17 wherein said at least one interchangeable FEC error checking encoder is configured with software to perform the BCH error checking protocol to create at least one telemetry data signal.

26. The telemetry system of claim 17 wherein said at least one interchangeable FEC error checking encoder is configured with software to perform the pseudo randomization error checking protocol to create at least one telemetry data signal.