Data storage device having multiple removable memory boards
First Claim
Patent Images
1. A data storage device comprising:
- a first memory board;
a second memory board, wherein;
the first memory board and the second memory board each comprise multiple memory chips; and
a controller board that is arranged and configured to operably connect to the first memory board and the second memory board, wherein the controller board comprises;
an interface, anda controller that is arranged and configured to receive commands from a host using the interface and to execute the commands, wherein the controller comprises;
multiple channels, wherein each of the channels is associated with one or more of the memory chips and each of the memory chips is associated with one of the channels, andmultiple channel controllers, wherein each channel controller is assigned to one of the multiple channels and is configured to process commands designated for the memory chips associated with the assigned channel,wherein the first memory board and the second memory board are each separately removable from the controller board and the first memory board, the second memory board and the controller board are assembled together to form a form factor that is sized to fit in a drive bay of a computing device with the first memory board connected to a top side of the controller board using a ball grid array connector and the second memory board connected to a bottom side of the controller board using a ball grid array connector such that the first memory board, the controller board and the second memory board form the form factor.
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Accused Products
Abstract
A data storage device may include a first memory board and a second memory board, where the first memory board and the second memory board each comprise multiple memory chips. The data storage device may include a controller board that is arranged and configured to operably connect to the first memory board and the second memory board, where the controller board includes a high speed interface and a controller that is arranged and configured to receive commands from a host using the high speed interface and to execute the commands, where the first memory board and the second memory board are each separately removable from the controller board.
189 Citations
26 Claims
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1. A data storage device comprising:
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a first memory board; a second memory board, wherein; the first memory board and the second memory board each comprise multiple memory chips; and a controller board that is arranged and configured to operably connect to the first memory board and the second memory board, wherein the controller board comprises; an interface, and a controller that is arranged and configured to receive commands from a host using the interface and to execute the commands, wherein the controller comprises; multiple channels, wherein each of the channels is associated with one or more of the memory chips and each of the memory chips is associated with one of the channels, and multiple channel controllers, wherein each channel controller is assigned to one of the multiple channels and is configured to process commands designated for the memory chips associated with the assigned channel, wherein the first memory board and the second memory board are each separately removable from the controller board and the first memory board, the second memory board and the controller board are assembled together to form a form factor that is sized to fit in a drive bay of a computing device with the first memory board connected to a top side of the controller board using a ball grid array connector and the second memory board connected to a bottom side of the controller board using a ball grid array connector such that the first memory board, the controller board and the second memory board form the form factor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computing device comprising:
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a host; and a data storage device, the data storage device comprising; a first memory board; a second memory board, wherein; the first memory board and the second memory board each comprise multiple memory chips; and a controller board that is arranged and configured to operably connect to the first memory board and the second memory board, wherein the controller board comprises; an interface, and a controller that is arranged and configured to receive commands from the host using the high speed interface and to execute the commands, wherein the controller comprises; multiple channels, wherein each of the channels is associated with one or more of the memory chips and each of the memory chips is associated with one of the channels, and multiple channel controllers, wherein each channel controller is assigned to one of the multiple channels and is configured to process commands designated for the memory chips associated with the assigned channel, wherein the first memory board and the second memory board are each separately removable from the controller board and the first memory board, the second memory board and the controller board are assembled together to form a form factor that is sized to fit in a drive bay of a computing device with the first memory board connected to a top side of the controller board using a ball grid array connector and the second memory board connected to a bottom side of the controller board using a ball grid array connector such that the first memory board, the controller board and the second memory board form the form factor. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for assembling a data storage device, the method comprising:
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securing multiple memory chips to a first memory board; securing multiple memory chips to a second memory board; attaching an interface and a controller to a controller board, wherein the controller comprises; multiple channels, wherein each of the channels is associated with one or more of the memory chips and each of the memory chips is associated with one of the channels, and multiple channel controllers, wherein each channel controller is assigned to one of the multiple channels and is configured to process commands designated for the memory chips associated with the assigned channel; operably connecting the first memory board to a top side of the controller board using a ball grid array connector; operably connecting the second memory board to a bottom side of the controller board using a ball grid array connector, wherein the first memory board and the second memory board are each separately removable from the controller board; and assembling the first memory board, the second memory board and the controller board to form a form factor that is sized to fit in a drive bay of a computing device. - View Dependent Claims (22, 23, 24, 25, 26)
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Specification