Method for wear leveling in a nonvolatile memory

• US 8,578,088 B2
• Filed: 09/21/2010
• Issued: 11/05/2013
• Est. Priority Date: 09/21/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Rousseau, Hubert
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US12/887,310
• Publication Number:
  US 20110072202A1
• Time in Patent Office: 1,141 Days
• Field of Search: 711/103, 711/154, 711/156, 711/206, 711/208, 711/209, 711/E12.016, 711/E12.017, 711/E12.022, 711/E12.059
• US Class Current: 711/113
• CPC Class Codes: G06F 11/1435 using file system or storage system metadata
• CPC Class Codes: G06F 11/1471 involving logging of persistent data for recovery
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written

Abstract

A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.

Claims

1. A method for writing and reading data in electrically erasable and programmable nonvolatile memory cells comprising:

defining data pages in a first nonvolatile memory zone;

defining in the data pages programmable data blocks;

defining in a second nonvolatile memory zone, metadata pages comprising metadata structures associated with the data pages present in the first nonvolatile memory zone and wherein each of the data pages is associated with a metadata structure of the metadata pages, each metadata structure including a wear counter containing a value representative of a number of times that the data page associated with the metadata structure has been erased;

attributing to each metadata page a wear counter containing a value representative of a number of times that a metadata page to which the wear counter is attributed has been erased;

arranging a wear counter of a metadata page inside the metadata page;

before erasing the metadata page, writing in the second nonvolatile memory zone a temporary information structure comprising;

an address in the second nonvolatile memory zone of the metadata page and a wear counter of the metadata page; and

after having erased the metadata page;

reading the wear counter from the temporary information structure;

incrementing the wear counter read from the temporary information structure; and

writing the incremented wear counter in the erased metadata page.

2. The method of claim 1, comprising:

writing, in each metadata structure associated with a data page, an information about a status, valid or invalid, of the data page; and

erasing data pages having a status of invalid as indicated in an associated metadata structure of the data page.

3. The method of claim 1, comprising:

invalidating a metadata structure associated with an erased data page;

attributing a new metadata structure to the erased data page; and

writing in the new metadata structure an incremented value of a wear counter present in the invalidated metadata structure.

4. The method of claim 1, comprising:

invalidating a metadata structure associated with an erased data page; and

erasing a metadata page that has only invalid metadata structures.

5. The method of claim 4, comprising:

invalidating a metadata page that has only invalid metadata structures; and

erasing the invalidated metadata page after the invalidated metadata page becomes invalid.

6. The method of claim 1, comprising:

dynamically managing page wear, the dynamically managing comprising;

when data is to be written in a new data page of the first nonvolatile memory zone, selecting, from among several erased data pages of the first nonvolatile memory zone, a data page having a lowest wear counter; and

writing the data in the selected data page.

7. The method of claim 1, comprising:

dynamically managing page wear, the dynamically managing comprising;

generating a list of page addresses of erased data pages of the first nonvolatile memory zone;

classifying the addresses of the erased data pages in increasing or decreasing order according to values of wear counters in metadata structures associated with the erased data pages; and

when data is to be written in a new data page of the first nonvolatile memory zone, selecting, from the list of page addresses, an address of an erased data page based on the erased data page with the selected address having a wear counter value in an associated metadata structure that is lower than one or more other wear counter values in associated metadata structures of erased data pages having addresses in the list of page addresses; and

writing the data in the erased data page associated with the selected address.

8. The method of claim 1, comprising statically managing page wear, the statically managing page wear comprising transferring, into a second data page of the first nonvolatile memory zone, data present in a first data page, the second data page having a wear counter with a lower value than that of a wear counter of the first data page.

9. The method of claim 1, comprising:

configuring the metadata structures associated with the data pages in the form of descriptors, a descriptor being associated with a metadata structure that is associated with a data page, and including;

a metadata field for an associated wear counter included in the metadata structure associated with the data page;

a first field containing an address of an erasable data page in the first nonvolatile memory zone or an index indicating a position of the erasable data page in the first nonvolatile memory zone;

a second field containing an address of a logical page in a virtual memory or an index indicating a position of the logical page in a virtual memory; and

for each data block of the data page with which the descriptor is associated, a third field containing;

an information about a location of the data block, in the data page;

an information about a status of the data block the status being from a group having at least the three following statuses;

erased block, block containing a valid data, or block containing an invalid data; and

an information about a position in the logical page of data stored in the data block.

10. The method of claim 9, wherein the third field is a field of indexed metadata which designates a data block of the data page with which the descriptor is associated, and wherein contents of the indexed metadata has one of the following:

an erased value indicating that the designated block is erased, a programmed value indicating that the designated block contains an invalid data, or a partially programmed value giving an information about the position in the logical page of the data stored in the designated block.

11. The method of claim 1, comprising defining the first and second nonvolatile memory zones within one nonvolatile memory.

12. The method of claim 1, comprising:

in response to a read command of other data having a logical address;

finding, in the second nonvolatile memory zone, a metadata structure containing the logical address and associated with valid data;

reading, in the metadata structure found, an address of the other data in the first memory zone, and

reading the other data in the first nonvolatile memory zone.

13. The method of claim 1, comprising:

before writing, in the second nonvolatile memory zone, the address of the metadata page, writing in the temporary information structure a start flag, and

after having erased the wear counter of the metadata page, writing a final flag in the temporary information structure.

14. An integrated circuit comprising:

a processing unit; and

at least one nonvolatile memory, communicatively coupled to the processing unit, comprising electrically erasable and programmable memory cells, wherein the processing unit is configured to receive write or read commands and to execute commands that cause the following to be performed;

defining data pages in a first nonvolatile memory zone;

defining in the data pages programmable data blocks;

defining in a second nonvolatile memory zone, metadata pages comprising metadata structures associated with the data pages present in the first nonvolatile memory zone and wherein each of the data pages is associated with a metadata structure of the metadata pages, each metadata structure including a wear counter containing a value representative of a number of times that the data page associated with the metadata structure has been erased;

attributing to each metadata page a wear counter containing a value representative of a number of times that a metadata page to which the wear counter is attributed has been erased;

arranging a wear counter of a metadata page inside the metadata page;

before erasing the metadata page, writing in the second nonvolatile memory zone a temporary information structure comprising;

an address in the second nonvolatile memory zone of the metadata page and a wear counter of the metadata page; and

after having erased the metadata page;

reading the wear counter from the temporary information structure;

incrementing the wear counter read from the temporary information structure; and

writing the incremented wear counter in the erased metadata page.

15. The integrated circuit of claim 14, wherein the processing unit is further configured to execute commands that cause the following to be performed:

writing, in each metadata structure associated with a data page, an information about a status, valid or invalid, of the data page; and

erasing data pages having a status of invalid as indicated in an associated metadata structure of the data page.

16. The integrated circuit of claim 14, wherein the processing unit is further configured to execute commands that cause the following to be performed:

invalidating a metadata structure associated with an erased data page;

attributing a new metadata structure to the erased data page; and

writing in the new metadata structure an incremented value of a wear counter present in the invalidated metadata structure.

17. The integrated circuit of claim 14, wherein the processing unit is further configured to execute commands that cause the following to be performed:

in response to a read command of other data having a logical address;

finding, in the second nonvolatile memory zone, a metadata structure containing the logical address and associated with valid data;

reading, in the metadata structure found, an address of the other data in the first memory zone; and

reading the other data in the first nonvolatile memory zone.

18. The integrated circuit of claim 14, wherein the processing unit is further configured to execute commands that cause the following to be performed:

before writing, in the second nonvolatile memory zone, the address of the metadata page, writing in the temporary information structure a start flag, and

after having erased the wear counter of the metadata page, writing a final flag in the temporary information structure.

19. A portable device comprising:

a portable device housing; and

an integrated circuit within the housing, the integrated circuit comprising;

a processing unit; and

at least one nonvolatile memory, communicatively coupled to the processing unit, comprising electrically erasable and programmable memory cells, wherein the processing unit is configured to receive write or read commands and to execute commands that cause the following to be performed;

defining data pages in a first nonvolatile memory zone;

defining in the data pages programmable data blocks;

defining in a second nonvolatile memory zone, metadata pages comprising metadata structures associated with the data pages present in the first nonvolatile memory zone and wherein each of the data pages is associated with a metadata structure of the metadata pages, each metadata structure including a wear counter containing a value representative of a number of times that the data page associated with the metadata structure has been erased;

attributing to each metadata page a wear counter containing a value representative of a number of times that a metadata page to which the wear counter is attributed has been erased;

arranging a wear counter of a metadata page inside the metadata page;

before erasing the metadata page, writing in the second nonvolatile memory zone a temporary information structure comprising;

an address in the second nonvolatile memory zone of the metadata page and a wear counter of the metadata page; and

after having erased the metadata page;

reading the wear counter from the temporary information structure;

incrementing the wear counter read from the temporary information structure; and

writing the incremented wear counter in the erased metadata page.

20. The portable device of claim 19, wherein the processing unit is further configured to execute commands that cause the following to be performed:

writing, in each metadata structure associated with a data page, an information about a status, valid or invalid, of the data page; and

erasing data pages having a status of invalid as indicated in an associated metadata structure of the data page.

21. The portable device of claim 19, wherein the processing unit is further configured to execute commands that cause the following to be performed:

invalidating a metadata structure associated with an erased data page;

attributing a new metadata structure to the erased data page; and

writing in the new metadata structure an incremented value of a wear counter present in the invalidated metadata structure.

22. The portable device of claim 19, wherein the processing unit is further configured to execute commands that cause the following to be performed:

in response to a read command of other data having a logical address;

finding, in the second nonvolatile memory zone, a metadata structure containing the logical address and associated with valid data;

reading, in the metadata structure found, an address of the other data in the first memory zone; and

reading the other data in the first nonvolatile memory zone.

23. The portable device of claim 19, wherein the processing unit is further configured to execute commands that cause the following to be performed:

before writing, in the second nonvolatile memory zone, the address of the metadata page, writing in the temporary information structure a start flag, and

after having erased the wear counter of the metadata page, writing a final flag in the temporary information structure.