Reducing aging effect on registers

• US 8,578,137 B2
• Filed: 11/03/2006
• Issued: 11/05/2013
• Est. Priority Date: 11/03/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Abella, Jaume, Vera, Xavier, Gonzalez, Antonio
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US11/791,145
• Publication Number:
  US 20090150656A1
• Time in Patent Office: 2,559 Days
• Field of Search: 712/225, 712/32, 712/227
• US Class Current: 712/225
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

Methods and apparatus to reduce aging effect on registers are described. In one embodiment, a select value is stored in a register that is unused, for example, to reduce the effects of negative bias temperature instability (NBTI) or oxide degradation on the register. Other embodiments are also described.

Claims

1. A processor comprising:

a register to store data;

a counter to store a first value to indicate a dynamic time amount of how long a portion of the register has maintained an inverted versus a non-inverted value; and

a first logic to cause storage of a second value in the register in response to a detection that the register is to be released, wherein the first logic causes storage of the second value in the register in response to the first value indicating that the portion of the register has maintained an inverted value for a shorter time period than a non-inverted value.

2. The processor of claim 1, further comprising a second logic to update the second value on a periodic basis.

3. The processor of claim 1, further comprising a register file that comprises the register.

4. The processor of claim 3, further comprising a second logic to update the second value based on a value, written to one of a plurality of registers in the register file.

5. The processor of claim 1, further comprising a second logic to update the first value based on one or more accesses to the storage unit.

6. The processor of claim 1, wherein the storage unit comprises a plurality of bit cells and each bit cell of the storage unit comprises at least two transistors to store a bit of the data.

7. The processor of claim 1, wherein the storage unit comprises a static random access memory (SRAM) device.

8. The processor of claim 1, further comprising one or more processor cores, wherein at least one of the processor cores comprises the logic.

9. A method comprising:

detecting whether a register is released; and

storing a value in the register based on how long the register has stored an inverted value and a non-inverted value.

10. The method of claim 9, further comprising updating the stored value after determining that the register has stored an inverted value for a shorter time period than a non-inverted value.

11. The method of claim 9, further comprising updating the value on a periodic basis.

12. The method of claim 9, further comprising updating the value based on a value written to one of a plurality of registers in a register file.

13. The method of claim 9, wherein the storing is performed in response to a determination that a write port is available to write the value into the register.

14. A computing system comprising:

a memory to store data; and

a processor core comprising;

a register to store a portion of the data stored in the memory, wherein the register includes an inverted period field to store a value indicating how long the register has stored an inverted value and a non-inverted period field to store a value indicating how long the register has stored a non-inverted value; and

logic to cause storage of a value in the register in response to a detection that the register is to be released, wherein the logic causes storage of the value in the register in response to an indication that the register has maintained an inverted value for a shorter time period than a non-inverted value.

15. The system of claim 14, wherein the memory comprises a cache.

16. The system of claim 14, wherein the register comprises a plurality of p-channel metal-oxide semiconductor (P-MOS) or n-channel metal-oxide semiconductor (N-MOS) transistors.

17. The system of claim 14, further comprising logic to update the stored value based on a value written to one of a plurality of registers in a register file, wherein the register file comprises the register.

18. The system of claim 14, further comprising logic to update the stored value on a periodic basis.

19. The system of claim 14, further comprising a plurality of processor cores to access the data stored in the memory.

20. The system of claim 14, further comprising an audio device.

21. An apparatus comprising:

a first logic unit to invert values stored in a first register when the first register is not storing data to be used by a second logic unit; and

a second register to store inverted values to be stored in the first register to reduce an aging effect of the first register.

22. The apparatus of claim 21, wherein the first logic is to invert the values stored in the first register according to a first inversion period.

23. The apparatus of claim 22, wherein the inverted values are to be stored in the first register only if a write port to the first register is available.

24. The apparatus of claim 22, wherein the second logic includes a processor execution unit.

25. The apparatus of claim 24, wherein the first inversion period corresponds to 50% of the processor execution unit'"'"'s operation time.

26. The apparatus of claim 22, wherein the first logic includes an inversion logic and an inversion value update logic.

27. The apparatus of claim 22, wherein the first inversion period is to be measured by a first inversion counter coupled to the first register.