Apparatus and system for implementing variable speed scan testing
First Claim
1. A method for performing a scan test comprising:
- shifting a test vector that is at least n+m bits long into a clock control register that is m bits long, wherein n bits corresponds to scan test stimulus information and m bits correspond to clock information and wherein m bits of clock information are stored in the clock control register;
shifting n bits of the test vector into a register of scan chain in an integrated circuit;
generating a test clock signal at a predetermined frequency responsive to the m bits of clock information;
generating a launch signal responsive to the test clock signal; and
generating a capture signal responsive to the test clock signal, wherein the capture signal initiates operation to capture a response pattern of the integrated circuit.
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Abstract
In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency.
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Citations
10 Claims
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1. A method for performing a scan test comprising:
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shifting a test vector that is at least n+m bits long into a clock control register that is m bits long, wherein n bits corresponds to scan test stimulus information and m bits correspond to clock information and wherein m bits of clock information are stored in the clock control register; shifting n bits of the test vector into a register of scan chain in an integrated circuit; generating a test clock signal at a predetermined frequency responsive to the m bits of clock information; generating a launch signal responsive to the test clock signal; and generating a capture signal responsive to the test clock signal, wherein the capture signal initiates operation to capture a response pattern of the integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification