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Apparatus and system for implementing variable speed scan testing

  • US 8,578,226 B2
  • Filed: 08/17/2010
  • Issued: 11/05/2013
  • Est. Priority Date: 08/17/2010
  • Status: Expired due to Fees
First Claim
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1. A method for performing a scan test comprising:

  • shifting a test vector that is at least n+m bits long into a clock control register that is m bits long, wherein n bits corresponds to scan test stimulus information and m bits correspond to clock information and wherein m bits of clock information are stored in the clock control register;

    shifting n bits of the test vector into a register of scan chain in an integrated circuit;

    generating a test clock signal at a predetermined frequency responsive to the m bits of clock information;

    generating a launch signal responsive to the test clock signal; and

    generating a capture signal responsive to the test clock signal, wherein the capture signal initiates operation to capture a response pattern of the integrated circuit.

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