Programming error correction code into a solid state memory device with varying bits per cell

• US 8,578,244 B2
• Filed: 10/02/2012
• Issued: 11/05/2013
• Est. Priority Date: 06/12/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F., Sarin, Vishal, Hoei, Jung S.
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US13/633,158
• Publication Number:
  US 20130024736A1
• Time in Patent Office: 399 Days
• Field of Search: 714/768, 714/718, 714/764, 714/774, 714/799, 365/189.09, 365/201
• US Class Current: 714/768
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators

Abstract

Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Claims

1. A method comprising:

determining a level of reliability of an area of a memory array in which a block of data is stored; and

storing metadata associated with the block of data in one of the area of the memory array in which the block of data is stored or an area of the memory array near the area of memory array in which the block of data is stored in response to the level of reliability of the area of the memory array in which the block of data is stored being at least substantially equal to a desired level of reliability for the metadata.

2. A device, comprising:

an array of memory cells; and

control circuitry coupled to the array of memory cells wherein the control circuitry is configured to program metadata for a block of data by determining a desired level of reliability for the metadata, determining a memory area level of reliability, at a bit level, for a memory area of the array of memory cells in which the block of data is stored, storing the metadata with the block of data and at the bit level if the memory area level of reliability is at least substantially equal to the desired level of reliability, and storing the metadata to another area of the array of memory cells if the memory area level of reliability is less than the desired level of reliability.

3. A method comprising:

calibrating a controller to a reliability of an area of a memory array; and

changing a bit level of ECC data and/or metadata programmed into the area of the memory array based on the calibration and a desired level of reliability.

4. The method of claim 3 wherein calibrating the controller to a reliability of an area of the memory array comprises:

writing a first voltage to a center memory cell;

writing a second voltage to memory cells surrounding the center memory cell;

reading the center memory cell at a first time;

varying threshold voltages of the surrounding memory cells;

reading the center memory cell at a second time; and

generating a table comprising an indication of an ability of the center memory cell to retain the first voltage responsive to the varying of the threshold voltages of the surrounding memory cells.

5. The method of claim 3, wherein calibrating the controller comprises storing calibration data in memory that is accessible by the controller.

6. The method of claim 5, wherein the memory that is accessible by the controller is the memory array.

7. The method of claim 3, wherein calibrating the controller comprises performing a calibration method on representative memory cells of different areas of the memory array.

8. The method of claim 3, wherein calibrating the controller comprises calibrating the controller at power-up of a memory device including the memory array.

9. The method of claim 3, wherein changing the bit level comprises programming ECC data into the area of the memory array at a bit level per memory cell determined by an actual error rate of the area.

10. The method of claim 3, wherein changing the bit level comprises programming metadata into the area of the memory array at a bit level per memory cell determined by an actual error rate of the area.

11. A method comprising:

determining a respective error rate for each of a plurality of areas of a memory array; and

determining in which of the plurality of areas to store ECC data and/or metadata based on the determined respective error rates.

12. The method of claim 11, wherein determining the respective error rate comprises accessing calibration data from a table in memory.

13. The method of claim 11, wherein determining the respective error rate comprises performing a calibration method on representative memory cells of the plurality of areas of the memory array.

14. A method comprising:

determining an actual error rate of a memory cell in an area of a memory array; and

storing ECC data and/or metadata in the area of the memory array at a bit level per memory cell determined by the actual error rate of the memory cell.

15. A device comprising:

an array of memory cells; and

control circuitry coupled to the array of memory cells wherein the control circuitry is configured to calibrate a controller to a reliability of an area of the array of memory cells and change a bit level of ECC data and/or metadata programmed into the area of the array of memory cells based on the calibration and a desired level of reliability.

16. The device of claim 15, wherein the control circuitry is further configured to control calibration of the controller by controlling writing a first voltage to a center memory cell of the array of memory cells, writing a second voltage to memory cells surrounding the center memory cell, reading the center memory cell at a first time, varying threshold voltages of the surrounding memory cells, reading the center memory cell at a second time, and generating a table comprising an indication of an ability of the center memory cell to retain the first voltage responsive to the varying of the threshold voltages of the surrounding memory cells.

17. The device of claim 16, wherein the control circuitry is further configured to calibrate the controller by storing calibration data in memory that is accessible by the controller.

18. The device of claim 17, wherein the memory that is accessible by the controller is the memory array.

19. A device comprising:

an array of memory cells; and

control circuitry coupled to the array of memory cells wherein the control circuitry is configured to determine a respective error rate for each of a plurality of areas of the array of memory cells and determine in which of the plurality of areas to store ECC data and/or metadata based on the determined respective error rates.

20. A device comprising:

an array of memory cells; and

control circuitry coupled to the array of memory cells wherein the control circuitry is configured to determine an actual error rate of a memory cell in an area of the array of memory cells and store ECC data and/or metadata in the area of the array of memory cells at a bit level per memory cell determined by the actual error rate of the memory cell.