Parallel decoding scheme for an indicia reader

• US 8,579,200 B2
• Filed: 11/05/2012
• Issued: 11/12/2013
• Est. Priority Date: 01/15/2010
• Status: Active Grant

• Current Assignee: Hand Held Products Incorporated (Honeywell International Inc.)
• Original Assignee: Hand Held Products Incorporated (Honeywell International Inc.)
• Inventors: Samek, Justin, Nahill, James A.
• Primary Examiner(s): Labaze, Edwyn
• Application Number:
  US13/668,956
• Publication Number:
  US 20130240626A1
• Time in Patent Office: 372 Days
• Field of Search: 235/470, 235/487, 235/462.1, 235/375, 235/454, 235/462.07
• US Class Current: 235/470
• CPC Class Codes: G06K 7/10821 further details of bar or optical code scanning devices
• CPC Class Codes: G06K 7/1092 sensing by means of TV-scanning
• CPC Class Codes: G06K 7/14 using light without selection of wavelength, e.g. sensing reflected white light G06K7/10831 - G06K7/1097 take precedence

Abstract

A method for collecting and processing information bearing indicia (IBI) comprising the steps of: converting light reflected off an IBI into IBI signals representative of the IBI; running at least one signal process for processing the IBI signals on a first processor if the IBI is of a first type; and running at least one signal process for processing the IBI signals on a second processor if the IBI is of a second type, wherein the first processor and second processor are configured to run in parallel.

Claims

1. An apparatus for collecting and processing information bearing indicia (IBI) comprising:

a hand held housing;

a converter for converting light reflected off an IBI into IBI signals representative of the IBI;

a first processor configured for running a first signal process for processing the IBI signals if the IBI is of a first type; and

a second processor configured for running a second signal process for processing the IBI signals if the IBI is of a second type,

wherein the first processor and second processor run the first and second signal processes in parallel and independent of each other, and

wherein at least a portion of the processing may be achieved via multiprocessing, where different processing threads run simultaneously on the same processor.

2. An apparatus in accordance with claim 1, wherein the IBI of a first type is a 1D symbol and the IBI of a second type is a 2D symbol.

3. An apparatus in accordance with claim 1, wherein the first and second processors are part of a multi-core processor having multiple logic units on one substrate.

4. An apparatus in accordance with claim 1, wherein signal processes comprise at least one of the following:

decoding;

image processing and signal processing.

5. An apparatus in accordance with claim 1, wherein the converting is accomplished utilizing a linear image sensor or an image sensor array.

6. An apparatus in accordance with claim 1, wherein the first and second processors are configured to run in parallel through a common communications link.

7. An apparatus in accordance with claim 1, wherein the first and second processors are connected by an array of common memory.

8. An apparatus for collecting and processing information bearing indicia (IBI) comprising:

a hand held housing;

a converter for converting light reflected off an IBI into IBI signals representative of the IBI;

a first processor configured for running a first signal process for processing the IBI signals if the IBI is of a first type; and

a second processor configured for running a second signal process for processing the IBI signals if the IBI is of a second type,

wherein the first processor and second processor run the first and second signal processes in parallel and independent of each other, and

wherein at least a portion of the processing may be achieved via multiprocessing, where different processing threads run consecutively on the same processor.

9. An apparatus in accordance with claim 8, wherein the IBI of a first type is a 1D symbol and the IBI of a second type is a 2D symbol.

10. An apparatus in accordance with claim 8, wherein the first and second processors are part of a multi-core processor having multiple logic units on one substrate.

11. An apparatus in accordance with claim 8, wherein signal processes comprise at least one of the following:

decoding;

image processing and signal processing.

12. An apparatus in accordance with claim 8, wherein the converting is accomplished utilizing a linear image sensor or an image sensor array.

13. An apparatus in accordance with claim 8, wherein the first and second processors are configured to run in parallel through a common communications link.

14. An apparatus in accordance with claim 8, wherein the first and second processors are connected by an array of common memory.