Semiconductor chip arrangement with sensor chip and manufacturing method

• US 8,580,613 B2
• Filed: 06/16/2009
• Issued: 11/12/2013
• Est. Priority Date: 06/17/2008
• Status: Active Grant

• Current Assignee: TDK Corporation
• Original Assignee: Epcos AG (TDK Corporation)
• Inventors: Feiertag, Gregor, Krueger, Hans, Leidl, Anton, Stelzl, Alois
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US12/999,421
• Publication Number:
  US 20110233690A1
• Time in Patent Office: 1,610 Days
• Field of Search: 257/414, 257/686, 257/723, 257/E23.142, 257/E23.178, 257/E25.006, 257/E25.013, 257/E31.111, 257/E31.113, 438/109
• US Class Current: 438/109
• CPC Class Codes: G01L 19/141 Monolithic housings, e.g. molded or one-piece housings
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

On a carrier (1) an adhesion layer (4), an ASIC chip (2) and a sensor chip (3) are arranged one above another. An interchip connection (5) is provided for electrically connecting the chips among one another, and an ASIC connection (6) is provided for externally electrically connecting the circuit integrated in the ASIC chip.

Claims

1. A method for manufacturing a semiconductor chip arrangement, the method comprising

fitting an ASIC chip on a carrier by means of an adhesion layer,

providing an ASIC connection for externally electrically connecting a circuit integrated in the ASIC chip,

arranging a sensor chip above a top side of the ASIC chip, said top side facing away from the carrier, and is permanently connected to the ASIC chip, and

producing an electrical connection between the sensor chip and connection contact areas on the top side of the ASIC chip, wherein the electrical connection is a direct inter-chip connection between the sensor chip and the ASIC chip wherein the electrical connection is formed by solder balls or stud bumps soldered or welded on the connection contact areas of the ASIC chip.

2. The method as claimed in claim 1, wherein

the electrical connection between the sensor chip and the ASIC chip is produced by means of solder balls.

3. The method as claimed in claim 1, wherein

the electrical connection between the sensor chip and the ASIC chip is produced by means of stud bumps.

4. The method as claimed in claim 1, further comprising

arranging the ASIC chip in a cutout in the carrier.

5. The method as claimed in claim 1, further comprising

covering the sensor chip with a decomposable covering layer and then embedded into a filling, and

removing the covering layer to an extent such that the sensor chip is separated from the filling by an interspace.

6. The method as claimed in claim 1, further comprising

applying an adhesive layer to the carrier, and

fixing the ASIC chip on the adhesive layer, such that the adhesive layer forms the adhesion layer.

7. The method as claimed in claim 1, further comprising

applying an adhesive film to the ASIC chip and

fixing the ASIC chip on the carrier by means of the film, such that the film forms the adhesion layer.

8. The method of claim 1, wherein the sensor chip is arranged above the top side of the ASIC chip by flip-chip mounting.

9. A method for manufacturing a semiconductor chip arrangement, the method comprising

fitting an ASIC chip on a carrier by means of an adhesion layer,

providing an ASIC connection for externally electrically connecting a circuit integrated in the ASIC chip,

arranging a sensor chip above a top side of the ASIC chip, said top side facing away from the carrier, and is permanently connected to the ASIC chip,

producing a direct electrical connection between the sensor chip and the ASIC chip,

covering the sensor chip with a decomposable covering layer and then embedded into a filling, and

removing the covering layer to an extent such that the sensor chip is separated from the filling by an interspace.