Thin film transistor substrate and display device including the same, and method for manufacturing thin film transistor substrate

• US 8,580,623 B2
• Filed: 11/10/2011
• Issued: 11/12/2013
• Est. Priority Date: 11/17/2010
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Tomiyasu, Kazuhide, Kimura, Tomohiro
• Primary Examiner(s): Parendo, Kevin
• Assistant Examiner(s): Vu, Pauline
• Application Number:
  US13/885,768
• Publication Number:
  US 20130234137A1
• Time in Patent Office: 733 Days
• Field of Search: 438/149
• US Class Current: 438/149
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A TFT (20) includes a semiconductor layer (12s1) of an oxide semiconductor, a source electrode (13sd) and a drain electrode (13dd) provided on the semiconductor layer (12s1) and separated from each other, a gate insulating film (15) covering a portion of the semiconductor layer between the source electrode (13sd) and the drain electrode (13dd), a gate electrode (18gd) provided over the semiconductor layer (12s1) with the gate insulating film (15) being interposed between the gate electrode (18gd) and the semiconductor layer (12s1). The source electrode (13sd) is integrally formed with the source line (13s1). The gate electrode (18gd) is integrally formed with the gate line (18g1). The semiconductor layer (12s1) extends below the source line (13s1). The entireties of the source line (13s1), the source electrode (13sd), and the drain electrode (13dd) are provided on the semiconductor layer (12s1).

Claims

1. A method for manufacturing a thin film transistor substrate including:

a base substrate;

source lines provided on the base substrate and extending in parallel to each other;

gate lines extending in parallel to each other in a direction intersecting the source lines;

thin film transistors, pixel electrodes, semiconductor layers, source electrodes, drain electrodes, and gate electrodes, wherein at each intersection portions of the source lines and the gate lines, there is one of the thin film transistors and one of the pixel electrodes,

each of the thin film transistors including one of the semiconductor layers of an oxide semiconductor, one of the source electrodes and one of the drain electrodes provided on the one of the semiconductor layers and separated from each other, a gate insulating film covering the semiconductor layers between the source and drain electrodes, and one of the gate electrodes provided over the one of the semiconductor layers with the gate insulating film being interposed between the one of the gate electrodes and the one of the semiconductor layers,

each of the source electrodes being integrally formed with a corresponding one of the source lines, each of the gate electrodes being integrally formed with a corresponding one of the gate lines, and each of the semiconductor layers extending below the corresponding one of the source lines, and

an entirety of each of the source lines, an entirety of each of the source electrodes, and an entirety of each of the drain electrodes being provided on a corresponding one of the semiconductor layers,

the method comprising;

a first patterning step of successively forming a semiconductor film of an oxide semiconductor and a first conductive film on the base substrate to form a first multilayer film, forming, on a semiconductor layer formation portion of the first multilayer film, a first resist pattern which is thicker in portions in which the source lines, the source electrodes, and the drain electrodes are to be formed than in other portions, using a multitone mask as a first photomask, and thereafter, patterning the first multilayer film using the first resist pattern as a mask, thereby forming the source lines and the semiconductor layers to be covered by a first conductive layer wherein the first conductive layer is integrated with the source lines;

a second patterning step of reducing a thickness of the first resist pattern to expose a portion of the first conductive layer in an area other than where the source electrodes and the drain electrodes are to be formed while leaving first the resist pattern only on the source lines and the portions in which the source and drain electrodes are to be formed, thereby forming a second resist pattern, and thereafter, patterning the first conductive layer using the second resist pattern as a mask, to form the source and drain electrodes;

a third patterning step of, after the second patterning step, forming the gate insulating film to cover the semiconductor layers, the source lines, the source electrodes, and the drain electrodes, and forming a third resist pattern on portions of the gate insulating film other than the drain electrodes, using a second photomask, and thereafter, patterning the gate insulating film using the third resist pattern as a mask, to form, in the gate insulating film, contact holes reaching the drain electrodes;

a fourth patterning step of successively forming a second conductive film and a third conductive film to cover the gate insulating film, thereby forming a second multilayer film, forming a fourth resist pattern which is thicker in portions in which the gate lines and the gate electrodes are to be formed than in other portions, using a multitone mask as a third photomask, and thereafter, patterning the second multilayer film using the fourth resist pattern as a mask, to form the gate lines, the gate electrodes, and the pixel electrodes, wherein the pixel electrodes are covered by a second conductive layer formed by a part of the third conductive film and connected through the contact holes to the drain electrodes; and

a fifth patterning step of reducing a thickness of the fourth resist pattern to expose the second conductive layer on the pixel electrodes while leaving the fourth resist pattern only on the gate lines and the gate electrodes, thereby forming a fifth resist pattern, and thereafter, removing the second conductive layer using the fifth resist pattern as a mask, to expose the pixel electrodes.

2. The method of manufacturing the thin film transistor substrate of claim 1, wherein

each of the pixel electrodes is connected to a surface of the drain electrodes of the thin film transistors through one of the contact holes formed in the gate insulating film, and

the gate lines and the gate electrodes each have a multilayer structure including a conductive layer and another conductive layer layered on the conductive layer, wherein the conductive layer is made of the same material as the pixel electrodes.

3. The method of manufacturing the thin film transistor substrate of claim 2, wherein

the another conductive layer has a same shape as the conductive layer.

4. The method of manufacturing the thin film transistor substrate of claim 2, wherein

each of the semiconductor layers is formed of an oxide semiconductor of indium gallium zinc oxide.