Metal oxide semiconductor transistor and method of manufacturing the same

• US 8,580,625 B2
• Filed: 07/22/2011
• Issued: 11/12/2013
• Est. Priority Date: 07/22/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lu, Tsuo-Wen, Lee, Tzung-Ying, Chen, Jei-Ming, Hsu, Chun-Wei, Lin, Yu-Min, Chang, Chia-Lung, Chien, Chin-Cheng, Chan, Shu-Yen
• Primary Examiner(s): Li, Meiya
• Application Number:
  US13/188,536
• Publication Number:
  US 20130020657A1
• Time in Patent Office: 844 Days
• Field of Search: 257/288, 257/368, 257/369, 257/374, 257/410, 257/E21.19, 257/E21.635, 257/E29.128, 438/151, 438/157, 438/176, 438/183, 438195-197, 438/218, 438/257, 438/278, 438/279, 438/283, 438/294, 438/585, 438/591, 438/595, 438/692
• US Class Current: 438/157
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor.

Claims

1. A method for manufacturing a MOS transistor, comprising:

forming a substrate, the substrate defining a first transistor region and a second transistor region and having a first opening and a second opening formed by removing a dummy gate, the substrate comprising a high-k dielectric layer and a barrier layer on the high-k dielectric layer in each of the first opening and the second opening;

forming a dielectric barrier layer on the substrate to fill into the first opening and the second opening and to cover the barrier layer;

removing a first portion of the dielectric barrier layer in the first transistor region so as to expose the barrier layer in the first opening;

forming a first work function metal layer on the substrate after removing the portion of the dielectric barrier layer in the first transistor region to fill into the first opening and the second opening;

removing the first work function metal layer in the second transistor region;

removing a second portion of the dielectric barrier layer in the second transistor region so as to expose the barrier layer in the second opening; and

forming a second work function metal layer on the substrate after removing the second portion of the dielectric barrier layer in the second transistor region to fill into the first opening and the second opening.

2. The method as claimed in claim 1, wherein the dielectric barrier layer is a silicon nitride layer.

3. The method as claimed in claim 2, wherein a thickness of the silicon nitride layer is in a range from 20 to 40 angstroms.

4. The method as claimed in claim 2, wherein the silicon nitride layer is formed by an atomic layer deposition process.

5. The method as claimed in claim 2, wherein the step of removing the first work function metal layer in the second transistor region comprises—

forming a third pattern photoresist layer on the first work function metal layer so that the first transistor region is covered by the third pattern photoresist layer and the second transistor region is exposed from the third pattern photoresist layer;

removing the first work function metal layer on the silicon nitride layer in the second transistor region; and

removing the third pattern photoresist layer after the step of removing the second portion of the dielectric barrier layer in the second transistor region.

6. The method as claimed in claim 1, wherein the first portion of the dielectric barrier layer in the first transistor region and the second portion of the dielectric barrier layer in the second transistor region each are removed by a dry etching process.

7. The method as claimed in claim 1, wherein the first work function metal layer in the second transistor region is removed by a wet etching process.

8. The method as claimed in claim 1, wherein the barrier layer is a titanium nitride layer.

9. The method as claimed in claim 1, wherein the first work function metal layer comprises titanium nitride, and the second work function metal layer comprises titanium aluminum.

10. The method as claimed in claim 1, wherein the step of forming the substrate further comprises:

forming an isolation structure in a silicon substrate so as to define the first transistor region and the second transistor region;

forming a first dummy gate structure and a second dummy gate structure on the silicon substrate, the first dummy gate structure and the second dummy gate structure locating in the first transistor region and the second transistor region respectively, and the first dummy gate structure and the second dummy gate structure each comprising the high-k dielectric layer, the barrier layer and the dummy gate on the barrier layer;

forming two spacers surrounding the first dummy gate structure and the second dummy gate structure respectively;

forming a dielectric layer on the silicon substrate to cover the first dummy gate structure, the second dummy gate structure and the two spacers;

applying a flattening process to the dielectric layer so as to expose the dummy gate in both the first transistor region and the second transistor region; and

removing the dummy gate to form the first opening in the first transistor region and the second opening in the second transistor region.

11. The method as claimed in claim 10, wherein the step of removing the first portion of the dielectric barrier layer in the first transistor region further comprises:

forming a first pattern photoresist layer on the dielectric barrier layer so that the second transistor region is covered by the first pattern photoresist layer and the first transistor region is exposed from the first pattern photoresist layer;

removing the dielectric barrier layer on the dielectric layer in the first transistor region and the dielectric barrier layer on the barrier layer and at a bottom of the first opening; and

removing the first pattern photoresist layer.

12. The method as claimed in claim 10, wherein before the step of removing the first work function metal layer in the second transistor region, the method further comprises an etch back process to remove the first work function metal layer on the dielectric layer in the first transistor region.

13. The method as claimed in claim 12, wherein the etch back process comprises:

forming a second pattern photoresist layer on the first work function metal layer so that the second transistor region is covered by the second pattern photoresist layer and the first transistor region is exposed from the second pattern photoresist layer;

removing the first work function metal layer on the dielectric layer in the first transistor region; and

removing the second pattern photoresist layer.

14. The method as claimed in claim 13, wherein the first work function metal layer on the dielectric barrier layer in the second transistor region is removed by a wet etching process.

15. The method as claimed in claim 1, further comprising forming a contact conductive layer after forming the second work function metal layer.

16. The method as claimed in claim 15, wherein the step of forming the contact conductive layer further comprises:

forming a low resistance conductive material layer to cover the second work function metal layer; and

performing a chemical mechanical polishing process to remove the low resistance conductive material layer outside the first opening and the second opening and the second work function metal layer outside the first opening and the second opening.

17. A method for manufacturing a MOS transistor, comprising:

forming a substrate having an opening, a high-k dielectric layer being disposed in the opening and is located at the bottom of the opening and a barrier layer being formed on the high-k dielectric layer;

forming a dielectric barrier layer on the substrate and filled into the opening to cover a sidewall of the opening and the barrier layer located at the bottom of the opening;

removing the dielectric barrier layer on the barrier layer located at the bottom of the opening so as to expose the barrier layer; and

forming a work function metal layer on the substrate and filled into the opening, the work function metal layer covering the dielectric barrier layer on the sidewall of the opening and covering the barrier layer located at the bottom of the opening.

18. The method as claimed in claim 17, wherein the dielectric barrier layer is a silicon nitride layer.

19. The method as claimed in claim 18, wherein a thickness of the silicon nitride layer is in a range from 20 to 40 angstroms.

20. The method as claimed in claim 18, wherein the silicon nitride layer is formed by an atomic layer deposition process.

21. The method as claimed in claim 17, wherein the dielectric barrier layer on the barrier layer located at the bottom of the opening is removed by a dry etching process.

22. The method as claimed in claim 17, wherein the barrier layer is a titanium nitride layer.

23. The method as claimed in claim 17, wherein the work function layer comprises a titanium aluminum layer.

24. The method as claimed in claim 17, wherein the work function layer comprises a titanium nitride layer and a titanium aluminum layer on the titanium nitride layer.

25. The method as claimed in claim 17, further comprising forming a contact conductive layer after forming the second work function metal layer.

26. The method as claimed in claim 25, wherein the step of forming the contact conductive layer further comprises:

forming a low resistance conductive material layer to cover the second work function metal layer; and

performing a chemical mechanical polishing process to remove the low resistance conductive material layer outside the first opening and the second opening and the second work function metal layer outside the first opening and the second opening.