Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material

• US 8,580,651 B2
• Filed: 12/21/2007
• Issued: 11/12/2013
• Est. Priority Date: 04/23/2007
• Status: Active Grant

• Current Assignee: IceMOS Technology Ltd
• Original Assignee: IceMOS Technology Ltd
• Inventors: Ishiguro, Takeshi
• Primary Examiner(s): SANDVIK, BENJAMIN P
• Application Number:
  US11/962,523
• Publication Number:
  US 20080258239A1
• Time in Patent Office: 2,153 Days
• Field of Search: None
• US Class Current: 438/433
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

Methods for manufacturing trench type semiconductor devices involve refilling the trenches after high temperature processing steps are performed. The methods allow thermally unstable materials to be used as refill materials for the trenches of the device. Trench type semiconductor devices containing thermally unstable refill materials are also provided. In particular, methods of manufacturing and devices of a trench type semiconductor devices containing organic refill materials are provided.

Claims

1. A method of manufacturing a trench type semiconductor device, the method comprising:

(i) providing a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having a heavily doped region of a first conductivity type at the second main surface and having a lightly doped region of the first conductivity type at the first main surface;

(ii) forming a terminal structure over the first main surface side, formation of the terminal structure including formation of;

(a) a gate electrode over the first main surface with a gate insulation layer interposed therebetween,

(b) a body region of a second conductivity type at the first main surface adjacent to the gate electrode,

(c) a source region of the first conductivity type in the body region, and

(d) a body contact of the second conductivity type in the body region adjacent to the source region;

(iii) after formation of the terminal structure, forming a mesa and a trench in the semiconductor substrate extending from the first main surface, with the terminal structure disposed generally over the mesa, the mesa being adjacent to the trench and having a first sidewall surface and a second sidewall surface;

(iv) doping, with a dopant of the second conductivity type opposite to the first conductivity type, the first sidewall surface;

(v) doping, with a dopant of the second conductivity type, the second sidewall surface;

(vi) driving in the dopant at the first and second sidewall surfaces to respectively form a first doped region of the second conductivity type and a second doped region of the second conductivity; and

(vii) following steps (i)-(vi), filling the trench with at least one of a semi-insulating material, an insulating material, and a combination thereof.

2. The method of claim 1, wherein the step of filling comprises filling the trench with at least one of a semi-insulating material and an insulating material that is thermally unstable at a temperature of about 800°

C. and above.

3. The method of claim 1, wherein the at least one of the semi-insulating material and the insulating material is thermally stable at a temperature selected from the group consisting of about 350°

C., about 400°

C., about 450°

C., about 500°

C., about 550°

C., about 600°

C., about 650°

C., about 700°

C., and about 750°

C.

4. The method of claim 1, wherein the at least one of the semi-insulating material and the insulating material is an organic material.

5. The method of claim 1, wherein the at least one of the semi-insulating material or the insulating material comprises polyimide.

6. The method of claim 1, wherein the step of filling comprises filling the trench with a material selected from the group consisting of a dielectric, undoped polysilicon, doped polysilicon, doped oxide, undoped oxide, silicon nitride, semi-insulating polycrystalline silicon (SIPOS), and a combination thereof.

7. The method of claim 1, further comprising, prior to the step of filling:

(viii) doping, with a dopant of the first conductivity type, the first sidewall surface to form a first doped region of the first conductivity type; and

(ix) doping, with a dopant of the first conductivity type, the second sidewall surface to form a second doped region of the first conductivity type.

8. The method of claim 1 further comprising smoothing the first and the second sidewall surfaces prior to the steps of doping.

9. The method of claim 1 further comprising lining the first and the second sidewall surfaces with at least one of an oxide material and a nitride material, prior to the filling step.

10. The method of claim 1, wherein the driving-in step comprises driving-in the dopant into the first and second sidewall surfaces at a temperature of about 900°

C. for about 1 hour.

11. The method of claim 1, wherein the doping step comprises one of ion implantation and diffusion.

12. The method of claim 1, wherein the trench is formed utilizing at least one of plasma etching, reactive ion etching (RIE), sputter etching, vapor phase etching, and chemical etching.

13. The method of claim 1, wherein a plurality of the terminal structures, a plurality of the mesas and a plurality of the trenches are provided.

14. The method of claim 1, wherein steps (i)-(vii) are performed sequentially.

15. The method of claim 1, wherein prior to commencement of each of the steps (i)-(vii), the respective preceding step is substantially completed.

16. The method of claim 1, wherein prior to commencement of each of the step, the preceding step is fully completed.

17. A trench type semiconductor device manufactured according to the method of claim 1.