Radiation detecting device and method of operating

• US 8,581,203 B2
• Filed: 09/13/2012
• Issued: 11/12/2013
• Est. Priority Date: 05/19/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: McCarthy, Michael
• Primary Examiner(s): Bryant, Casey
• Application Number:
  US13/613,448
• Publication Number:
  US 20130001428A1
• Time in Patent Office: 425 Days
• Field of Search: 25039001-39002
• US Class Current: 250/390.01
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A method of operating a radiation-detecting device includes charging a first charge storage region of a charge storage structure to place a first charge value at the first charge storage region, and charging a second charge storage region of the charge storage structure to place a second charge value at the second charge storage region. The method further includes conducting a first read operation to determine a change in the first charge value at the first charge storage region at a first time after charging the first charge storage region, and determining a first radiation flux value for an environment containing the charge storage structure based on the change in the first charge value at the first time.

Claims

1. A radiation-detecting device comprising:

a first multi-bit storage cell at a substrate comprising;

a first charge storage structure comprising a first nitride-containing layer overlying a first channel region at the substrate, the first charge storage structure configured to store a first electrical charge;

a first conductive gate layer overlying the first charge storage structure;

a first source/drain region adjacent the first channel region, wherein a portion of the first source/drain region underlies a portion of the first charge storage structure and a first bit storage region for storing information, wherein the first bit storage region is between the first source/drain region and the first conductive gate layer;

a second source/drain region adjacent the first channel region, wherein a portion of the second source/drain region underlies a portion of the first charge storage structure and a second bit storage region for storing information, wherein the second bit storage region is between the second source/drain region and the first conductive gate layer; and

a second multi-bit storage cell at the substrate comprising;

a second charge storage structure comprising a second nitride-containing layer overlying a second channel region at the substrate, the second charge storage structure configured to store a second electrical charge, wherein the second nitride-containing layer has an average thickness that is different than an average thickness of the first nitride-containing layer and a capacity to store electrical charge that is different than a capacity to store electrical charge of the first nitride-containing layer;

a second conductive gate layer overlying the second charge storage structure;

a third source/drain region adjacent the second channel region, wherein a portion of the third source/drain region underlies a portion of the second charge storage structure and a third bit storage region for storing information, wherein the third bit storage region is between the third source/drain region and the second conductive gate layer; and

a fourth source/drain region adjacent the second channel region, wherein a portion of the fourth source/drain region underlies a portion of the second charge storage structure and a fourth bit storage region for storing information, wherein the fourth bit storage region is between the fourth source/drain region and the second conductive gate layer.

2. The device of claim 1, wherein the first bit storage region and second bit storage region are contained within the first nitride-containing layer of the first charge storage structure.

3. The device of claim 2, further comprising a thermalizing layer overlying the first charge storage structure and not the second charge storage structure, the thermalizing layer configured to slow down a radiation.

4. The device of claim 1, wherein the second nitride-containing layer of the second charge storage structure has an average thickness that is greater than an average thickness of the nitride-containing layer of the first charge storage structure.

5. The device of claim 1, wherein the average thickness of the second nitride-containing layer is greater than average thickness of the first nitride-containing layer.

6. The device of claim 1, further comprising a thermalizing layer overlying the first charge storage structure and not the second charge storage structure, the thermalizing layer configured to slow down a radiation.

7. The device of claim 1 further comprising:

a control module coupled to the first multi-bit storage cell and to the second multi-bit storage cell to calculate a radiation flux in response to at least one of the charge storage structures having a different conductive state than expected.

8. The device of claim 7 wherein the control module is further to program each of the bit storage regions with a knowing amount of charge prior to calculating the radiation flux.

9. The device of claim 8, wherein the control module is further to determine at least one of the bit storage regions has been exposed to radiation event subsequent to being programmed to a knowing amount of charge, and prior to calculating the radiation flux.

10. The device of claim 1 further comprising;

the control module coupled to the first multi-bit storage cell and the second multi-bit storage cell to determine whether the device was exposed to a radiation event during a time that power was not applied to the device.

11. The device of claim 1, wherein the control module further comprises:

a timer used to determine read intervals during which each of the bit storage regions undergo read operations to determine if there has been a change in their program state.

12. A radiation-detecting device comprising:

a first charge storage structure having a first charge storage region overlying a first channel region at the substrate;

a first conductive gate layer overlying the first charge storage structure;

a first source/drain region and a second source/drain region adjacent the first channel region, wherein the first channel region is between the first and second source drain regions;

a second charge storage structure having a second charge storage region overlying a second channel region at the substrate;

a second conductive gate layer overlying the second charge storage structure;

a third source/drain region and a fourth source/drain region adjacent the second channel region, wherein the second channel region is between the third and fourth source drain regions;

a control module comprising;

program logic to program the first and second charge storage regions to a first charge value and to a second charge value, respectively;

read logic to apply a first read voltage to the first conductive gate layer to determine an amount of current generated by the first charge storage region responsive to the read voltage, and to apply a second read voltage to the second conductive gate layer to determine an amount of current generated by the second charge storage region responsive to the second read voltage; and

a logic module to determine a received amount of radiation based upon the difference between the amount of current generated by the first charge storage region and the amount off current generated by the second charge storage region, and to determine a first radiation flux for an environment containing the radiation-detecting device based on the received amount of radiation.

13. The device of claim 12, wherein the first charge storage structure is a first nitride-containing layer having a first average thickness, and the second charge storage structure is a second nitride-containing layer having a second average thickness that is more than the first average thickness.

14. The device of claim 12, wherein the first charge storage region comprises a charge storage capacity that is less than a charge storage capacity of the second charge storage region.

15. The device of claim 14, further comprising a thermalizing layer overlying the first charge storage structure, the thermalizing layer configured to slow down as radiation.

16. The device of claim 14, further comprising a thermalizing layer overlying the first charge storage structure and not the second charge storage structure, the thermalizing layer configured to slow down a radiation.

17. The device of claim 12, further comprising a thermalizing layer overlying the first charge storage structure and not the second charge storage structure, the thermalizing layer configured to slow down a radiation.

18. The device of claim 12, wherein the first charge storage structure further comprises a third charge storage region overlying the first channel region.

19. The device of claim 12, wherein the second charge storage structure further comprises a fourth charge storage region overlying the second channel region.

20. The device of claim 12, further comprising a shielding layer overlying the first charge storage structure and not the second charge storage structure.

21. A radiation-detecting device comprising:

a first multi-bit storage cell at a substrate comprising;

a first charge storage structure comprising a first nitride-containing layer overlying a first channel region at the substrate;

a first conductive gate layer overlying the first charge storage structure;

a first source/drain region adjacent the first channel region, wherein a portion of the first source/drain region underlies a portion of the first charge storage structure and a first bit storage region for storing information, wherein the first bit storage region is between the first source/drain region and the first conductive gate layer;

a second source/drain region adjacent the first channel region, wherein a portion of the second source/drain region underlies a portion of the first charge storage structure and a second bit storage region for storing information, wherein the second bit storage region is between the second source/drain region and the first conductive gate layer; and

a second multi-bit storage cell at the substrate comprising;

a second charge storage structure comprising a second nitride-containing layer overlying a second channel region at the substrate;

a second conductive gate layer overlying the second charge storage structure;

a third source/drain region adjacent the second channel region, wherein a portion of the third source/drain region underlies a portion of the second charge storage structure and a third bit storage region for storing information, wherein the third bit storage region is between the third source/drain region and the second conductive gate layer; and

a fourth source/drain region adjacent the second channel region, wherein a portion of the fourth source/drain region underlies a portion of the second charge storage structure and a fourth bit storage region for storing information, wherein the fourth bit storage region is between the fourth source/drain region and the second conductive gate layer; and

a thermalizing layer overlying the first charge storage structure and not the second charge storage structure, the thermalizing layer configured to slow down a radiation.