Nonvolatile semiconductor memory device and method of manufacturing same

• US 8,581,323 B2
• Filed: 03/19/2010
• Issued: 11/12/2013
• Est. Priority Date: 01/08/2010
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Higashi, Kazuyuki, Uenaka, Tsuneo
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US12/727,708
• Publication Number:
  US 20110169071A1
• Time in Patent Office: 1,334 Days
• Field of Search: 257/E21.677, 257/E21.679, 257/E27.103, 257/E29.103, 257/E29.17, 257/E29.309, 257314-326, 257E21662-E21678, 438/216, 438/261, 438/591, 438/593
• US Class Current: 257/316
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A memory string is formed to surround the side surface of a columnar portion and a charge storing layer, and includes plural first conductive layers functioning as gates of memory transistors, and a first protecting layer stacked to protect an upper portion of the plural first conductive layers. The plural first conductive layers constitute a first stairway portion formed stepwise such that their ends are located at different positions. Each first conductive layer constitutes a step of the first stairway portion. A top surface of a first portion of the first stairway portion is covered with the first protecting layer including a first number of layers, and A tope surface of a second portion of the first stairway portion located at a lower level than the first portion is covered with the first protecting layer including a second number of layers fewer than the first number of layers.

Claims

1. A nonvolatile semiconductor memory device, comprising a plurality of memory strings including a plurality of memory transistors connected in series, the memory transistors being electrically rewritable,

the memory strings including:

a first semiconductor layer including a columnar portion extending in a perpendicular direction relative to a substrate, the first semiconductor layer being configured to function as a body of the memory transistors;

a charge storing layer formed to surround a side surface of the columnar portion and configured to store a charge;

a plurality of first conductive layers formed to surround the side surface of the columnar portion and the charge storing layer and configured to function as gates of the memory transistors; and

a first protecting layer stacked to protect a top portion of the plurality of first conductive layers,

the plurality of first conductive layers constituting a first stairway portion formed stepwise such that ends of the first conductive layers are located at different positions, each of the first conductive layers constituting a step of the first stairway portion,

a top surface of a first portion of the first stairway portion being covered with the first protecting layer including a first number of layers, and

a top surface of a second portion of the first stairway portion being covered with the first protecting layer including a second number of layers fewer than the first number of layers, the second portion being located at a lower level than the first portion.

2. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of the first protecting layers are made of a same material.

3. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of the first protecting layers include a layer made of silicon nitride and a layer made of alumina.

4. The nonvolatile semiconductor memory device according to claim 1, wherein the plurality of steps are arranged side by side in one line in a predetermined direction parallel with the substrate.

5. The nonvolatile semiconductor memory device according to claim 1, wherein the plurality of steps are arranged in a matrix formation in a first direction and a second direction that are parallel with the substrate,

a plurality of the steps that are located at a first position in the first direction and arranged along the second direction have top surfaces covered with the first protecting layer including the first number of layers, and

a plurality of the steps that are located at a second position in the first direction and arranged along in the second direction have top surfaces covered with the first protecting layer including the second number of layers, the second position adjoining the first position.

6. The nonvolatile semiconductor memory device according to claim 1, further comprising a first selector transistor connected to one end of the memory strings,

wherein the first selector transistor includes:

a second semiconductor layer extending in the perpendicular direction from a top surface of the columnar portion and configured to function as a body of the first selector transistor;

a first gate insulating layer formed to surround a side surface of the second semiconductor layer; and

a second conductive layer formed to surround a side surface of the first gate insulating layer and configured to function as a gate of the first selector transistor.

7. The nonvolatile semiconductor memory device according to claim 6, wherein the second conductive layer has an end located at a position different from the positions of the ends of the first conductive layers, to constitute a step succeeding the first stairway portion.

8. The nonvolatile semiconductor memory device according to claim 6, wherein the first protecting layer is formed to cover the second conductive layer.

9. The nonvolatile semiconductor memory device according to claim 6, further comprising a second selector transistor connected to the other end of the memory strings,

wherein the second selector transistor includes:

a third semiconductor layer extending in the perpendicular direction from a bottom surface of the columnar portion and configured to function as a body of the second selector transistor;

a second gate insulating layer formed to surround a side surface of the third semiconductor layer; and

a third conductive layer formed to surround a side surface of the second gate insulating layer and configured to function as a gate of the second selector transistor.

10. The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor layer includes a joining portion joining bottom ends of a pair of the columnar portions.

11. The nonvolatile semiconductor memory device according to claim 10, further comprising:

a first selector transistor connected to one end of the memory strings; and

a second selector transistor connected to the other end of the memory strings,

wherein the first selector transistor includes;

a second semiconductor layer extending in the perpendicular direction from a top surface of one of the pair of columnar portions and configured to function as a body of the first selector transistor;

a first gate insulating layer formed to surround a side surface of the second semiconductor layer; and

a second conductive layer formed to surround a side surface of the first gate insulating layer and configured to function as a gate of the first selector transistor, and

wherein the second selector transistor includes;

a third semiconductor layer extending in the perpendicular direction from a top surface of the other of the pair of columnar portions and configured to function as a body of the second selector transistor;

a second gate insulating layer formed to surround a side surface of the third semiconductor layer; and

a third conductive layer formed to surround a side surface of the second gate insulating layer and configured to function as a gate of the second selector transistor.

12. The nonvolatile semiconductor memory device according to claim 11, wherein the second conductive layer and the third conductive layer have respective ends located at a position different from the positions of the ends of the first conductive layers, to form a step succeeding the first stairway portion.

13. The nonvolatile semiconductor memory device according to claim 11, wherein the first protecting layer is formed to cover the second conductive layer and the third conductive layer.

14. The nonvolatile semiconductor memory device according to claim 1, further comprising a control circuit configured to control the memory strings,

wherein the control circuit includes:

a plurality of fourth conductive layers formed in same layers as the plurality of first conductive layers; and

a second protecting layer stacked to protect a top portion of the plurality of fourth conductive layers.

15. The nonvolatile semiconductor memory device according to claim 14, wherein the control circuit further includes:

a diffused layer provided on the substrate and configured to function as a source/drain of a transistor;

a contact plug layer extending in the perpendicular direction from the diffused layer; and

an interlayer insulating layer surrounding the contact plug layer,

wherein the plurality of fourth conductive layers surround the interlayer insulating layer.

16. The nonvolatile semiconductor memory device according to claim 14, wherein the plurality of fourth conductive layers constitute a second stairway portion formed stepwise such that ends of the fourth conductive layers are located at different positions.

17. The nonvolatile semiconductor memory device according to claim 16, wherein a top surface of a first portion of the second stairway portion is covered with the second protecting layer including a first number of layers, and

a top surface of a second portion of the second stairway portion is covered with the second protecting layer including a second number of layers fewer than the first number of layers, the second portion being located at a lower level than the first portion.