Semiconductor memory device

• US 8,581,346 B2
• Filed: 06/24/2010
• Issued: 11/12/2013
• Est. Priority Date: 07/20/2009
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoon, HongSik, Zhao, Jinshi, Baek, Ingyu, Sim, Hyunjun, Park, Minyoung
• Primary Examiner(s): Menz, Laura M
• Assistant Examiner(s): Malek, Maliheh
• Application Number:
  US12/822,302
• Publication Number:
  US 20110012081A1
• Time in Patent Office: 1,237 Days
• Field of Search: 977/742, 257E27084-E27103, 257/68, 257/296, 257/368, 257/E21.209, 257E21645-E21694, 438/3, 438/57
• US Class Current: 257/368
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8418 adapted for focusing electric field or current, e.g. tip-shaped
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/883 Oxides or nitrides

Abstract

A semiconductor memory device includes a first conductive line, a second conductive line crossing over the first conductive line, a resistance variation part disposed at a position in which the second conductive line intersects with the first conductive line and electrically connected to the first conductive line and the second conductive line and a mechanical switch disposed between the resistance variation part and the second conductive line. The mechanical switch includes a nanotube.

Claims

1. A semiconductor memory device comprising:

a first conductive line;

a second conductive line crossing over the first conductive line;

a resistance variation part disposed at a position in which the second conductive line intersects with the first conductive line and electrically connected to the first conductive line and the second conductive line;

a mechanical switch disposed between the resistance variation part and the second conductive line, wherein the mechanical switch includes a nanotube;

a conductive pad disposed between the resistance variation part and the second conductive line and having an upper portion on which the nanotube is disposed; and

an interlayer dielectric film which is disposed on only a portion of an upper surface of the conductive pad and which covers side walls of the first conductive line, the resistance variation part, and the conductive pad, wherein the interlayer dielectric film has a first opening art partially exposing the upper surface of the conductive pad, and wherein the nanotube is disposed in the first opening part.

2. The semiconductor memory device of claim 1, wherein the resistance variation part comprises one of:

a phase-change material film pattern;

a magnetic tunnel junction structure pattern including a pinned layer, a tunneling layer, and a free layer, which are sequentially stacked;

a metal oxide film pattern; and

a solid electrolyte film pattern.

3. The semiconductor memory device of claim 2, wherein the resistance variation part is the phase-change material film pattern, the semiconductor memory device further comprises a dielectric film that is disposed between the conductive pad and the phase-change material film pattern and has a contact window, and the conductive pad and the phase-change material film pattern contact each other through the contact window.

4. The semiconductor memory device of claim 2, wherein the resistance variation part is the solid electrolyte film pattern, and one of the conductive pad and the first conductive line comprises a metal film having a tendency to diffuse a metal ion into the solid electrolyte film pattern.

5. The semiconductor memory device of claim 1, wherein a second distance between a side wall of the first opening part and the second conductive line is greater than a first distance between the nanotube and the interlayer dielectric film.

6. The semiconductor memory device of claim 5, wherein the second distance is equal to or greater than two times the first distance.

7. The semiconductor memory device of claim 5, wherein the second conductive line comprises one of:

a second opening part disposed at a position in which the second opening part overlaps the first opening part, and having a greater width than that of the first opening part; and

a laterally curved region of a side surface surrounding a part of side walls of the first opening part.

8. The semiconductor memory device of claim 1, wherein, when a voltage is applied to the first conductive line and the second conductive line, the nanotube contacts the second conductive line to turn the mechanical switch on.

19. The semiconductor memory device of claim 1, wherein the interlayer dielectric film is in direct physical contact with the portion of the upper surface of the conductive pad and in direct physical contact with the side walls of the first conductive line, the resistance variation part, and the conductive pad.

9. A semiconductor memory device comprising:

a buffer film disposed on a semiconductor substrate;

a first conductive line extending across the semiconductor substrate and disposed on the buffer layer;

a resistance variation part disposed on the first conductive line;

a conductive pad disposed on the resistance variation part;

an interlayer dielectric film which is disposed on only a portion of an upper surface of the conductive pad and covering sidewalls of the first conductive line, the resistance variation part and the conductive pad, wherein the interlayer dielectric film includes a first opening part that partially exposes the upper surface of the conductive pad;

a second conductive line that extends on the interlayer dielectric film and crosses an upper side of the first conductive line; and

a mechanical switch comprising a plurality of carbon nanotubes which are vertically elongated and disposed on the upper surface of the conductive pad exposed by the first opening part.

10. The semiconductor memory device of claim 9, wherein the second conductive line has a second opening part that overlaps the first opening part and is wider than the first opening part.

11. The semiconductor memory device of claim 9, wherein the resistance variation part includes a pinned layer, a tunneling layer and a free layer which are sequentially stacked on the first conductive line.

12. The semiconductor memory device of claim 11, wherein the pinned layer is an anti-ferromagnetic layer, the free layer is a ferromagnetic layer and the tunneling layer is an aluminum oxide film.

13. The semiconductor memory device of claim 9, wherein the resistance variation part comprises a first layer, a second layer and a third layer sequentially stacked on the first conductive line, the first layer is a first electrode, the third layer is a second electrode and the second layer is a metal oxide film pattern or a solid electrolyte film pattern.

14. The semiconductor memory device of claim 13, wherein the solid electrolyte film pattern comprises one of gennanium telluride (GeTe), antimony telluride (SbTe) and germanium antimony telluride (GeSbTe).

15. The semiconductor memory device of claim 9, further comprising a dielectric film disposed between the resistance variation part and the conductive pad, wherein the dielectric film includes a contact window, wherein the resistance variation part contacts the conductive pad through the contact window and wherein a dielectric spacer is disposed on a side wall of the contact window.

16. The semiconductor memory device of claim 15, wherein the dielectric film and the resistance variation part have line shapes that overlap the first conductive line.

17. The semiconductor memory device of claim 9, wherein the second conductive line includes a laterally curved region in side surfaces of the second conductive line, which surround a part of sidewalls of the first opening part and wherein a second distance between the side wall of the first opening part and the second conductive line is greater than a first distance between the nanotubes and the side wall of the first opening part.

18. The semiconductor memory device of claim 9, wherein the second conductive line extends in a straight line shape near a side surface of the first opening part.

20. The semiconductor memory device of claim 9, wherein the interlayer dielectric film is in direct physical contact with the portion of the upper surface of the conductive pad and in direct physical contact with the side walls of the first conductive line, the resistance variation part, and the conductive pad.