3D memory semiconductor device and structure

• US 8,581,349 B1
• Filed: 05/02/2011
• Issued: 11/12/2013
• Est. Priority Date: 05/02/2011
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Sekar, Deepak C., Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Schoenholtz, Joseph
• Application Number:
  US13/099,010
• Time in Patent Office: 925 Days
• Field of Search: None
• US Class Current: 257/402
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/36 : the transistor being a FinFET
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A 3D memory device, including: a first memory layer including a first memory transistor with side gates; a second memory layer including a second memory transistor with side gates; and a periphery circuits layer including logic transistors for controlling the memory, the periphery circuits are covered by a first isolation layer, where the first memory layer includes a first monolithically mono-crystal layer directly bonded to a second isolation layer, and the second memory layer includes a second monolithically mono-crystal layer directly bonded to the second isolation layer, and the first mono-crystal layer is bonded on top of the first isolation layer, and the second memory transistor is self-aligned to the first memory transistor.

Claims

1. A 3D memory device, comprising:

a first memory layer comprising a first memory transistor with side gates;

a second memory layer comprising a second memory transistor with side gates; and

a periphery circuits layer comprising logic transistors for controlling said memory, said periphery circuits are covered by a first isolation layer,

wherein said first memory layer comprises a first monolithically mono-crystal layer directly bonded to a second isolation layer, and

said second memory layer comprises a second monolithically mono-crystal layer directly bonded to said second isolation layer, and

said first mono-crystal layer is bonded on top of said first isolation layer, and

said second memory transistor is self-aligned to said first memory transistor, and

said first memory transistor and said second memory transistor each being a fully depleted mono-crystal silicon-on-insulator transistor with an undoped channel.

2. A 3D memory device according to claim 1, wherein said first memory transistor is non-volatile.

3. A 3D memory device according to claim 1, wherein at least one of said logic transistors is partially depleted.

4. A 3D memory device according to claim 1, further comprising:

at least one periphery transistor constructed above said second memory layer.

5. A 3D memory device according to claim 1, wherein said first memory layer comprises floating gate transistors.

6. A 3D memory device according to claim 1,

wherein said first memory layer comprises floating body transistors.

7. A 3D memory device according to claim 1, further comprising:

a vertical control line connecting at least one of said logic transistors to said first memory transistor.

8. A 3D memory device, comprising:

a first memory layer comprising a first memory transistor with side gates;

a second memory layer comprising a second memory transistor with side gates; and

a periphery circuits layer comprising logic transistors for controlling said memory, said periphery circuits are covered by a first isolation layer,

wherein said first memory layer comprises a first monolithically mono-crystal layer directly bonded to a second isolation layer, and

said second memory layer comprises a second monolithically mono-crystal layer directly bonded to said second isolation layer, and

said first mono-crystal layer is bonded on top of said first isolation layer, and

said second memory transistor is self-aligned to said first memory transistor.

9. A 3D memory device according to claim 8, wherein said first memory transistor and said second memory transistor each being a non-volatile transistor.

10. A 3D memory device according to claim 8, further comprising:

a second periphery layer comprising periphery circuits, said second periphery layer constructed above the second memory layer.

11. A 3D memory device according to claim 8, wherein said first memory layer comprises resistive-random access memory cells (R-RAM).

12. A 3D memory device according to claim 8, further comprising:

a vertical control line connecting at least one of said logic transistors to said first memory transistor.

13. A 3D memory device, comprising:

a first memory layer comprising a first memory transistor with side gates;

a second memory layer comprising a second memory transistor with side gates;

wherein said first memory layer comprises a first monolithically mono-crystal layer and a first isolation layer, and

said second memory layer comprises a second monolithically mono-crystal layer directly bonded to said first isolation layer, said second memory layer is covered by a second isolation layer, and

said second memory transistor is self-aligned to said first memory transistor;

a periphery circuits layer comprising logic transistors used for controlling said memory is bonded on top of said second isolation layer.

14. A 3D memory device according to claim 13, wherein said first memory layer comprises flash memory cells.

15. A 3D memory device according to claim 13, further comprising:

a second periphery layer comprising periphery circuits, said second periphery layer constructed underneath said first memory layer.

16. A 3D memory device according to claim 13, wherein

said first memory transistor and said second memory transistor share at least one side gate.

17. A 3D memory device according to claim 13, wherein said first memory layer comprises floating body memory cells.

18. A 3D memory device according to claim 13, wherein said first memory layer comprises resistive-random access memory cells (R-RAM).

19. A 3D memory device according to claim 13, wherein said first memory layer comprises floating gate transistors.

20. A 3D memory device according to claim 13, further comprising:

a vertical control line connecting at least one of said logic transistors to said first memory transistor.