3D memory semiconductor device and structure
First Claim
1. A 3D memory device, comprising:
- a first memory layer comprising a first memory transistor with side gates;
a second memory layer comprising a second memory transistor with side gates; and
a periphery circuits layer comprising logic transistors for controlling said memory, said periphery circuits are covered by a first isolation layer,wherein said first memory layer comprises a first monolithically mono-crystal layer directly bonded to a second isolation layer, andsaid second memory layer comprises a second monolithically mono-crystal layer directly bonded to said second isolation layer, andsaid first mono-crystal layer is bonded on top of said first isolation layer, andsaid second memory transistor is self-aligned to said first memory transistor, andsaid first memory transistor and said second memory transistor each being a fully depleted mono-crystal silicon-on-insulator transistor with an undoped channel.
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Accused Products
Abstract
A 3D memory device, including: a first memory layer including a first memory transistor with side gates; a second memory layer including a second memory transistor with side gates; and a periphery circuits layer including logic transistors for controlling the memory, the periphery circuits are covered by a first isolation layer, where the first memory layer includes a first monolithically mono-crystal layer directly bonded to a second isolation layer, and the second memory layer includes a second monolithically mono-crystal layer directly bonded to the second isolation layer, and the first mono-crystal layer is bonded on top of the first isolation layer, and the second memory transistor is self-aligned to the first memory transistor.
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Citations
20 Claims
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1. A 3D memory device, comprising:
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a first memory layer comprising a first memory transistor with side gates; a second memory layer comprising a second memory transistor with side gates; and a periphery circuits layer comprising logic transistors for controlling said memory, said periphery circuits are covered by a first isolation layer, wherein said first memory layer comprises a first monolithically mono-crystal layer directly bonded to a second isolation layer, and said second memory layer comprises a second monolithically mono-crystal layer directly bonded to said second isolation layer, and said first mono-crystal layer is bonded on top of said first isolation layer, and said second memory transistor is self-aligned to said first memory transistor, and said first memory transistor and said second memory transistor each being a fully depleted mono-crystal silicon-on-insulator transistor with an undoped channel. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A 3D memory device, comprising:
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a first memory layer comprising a first memory transistor with side gates; a second memory layer comprising a second memory transistor with side gates; and a periphery circuits layer comprising logic transistors for controlling said memory, said periphery circuits are covered by a first isolation layer, wherein said first memory layer comprises a first monolithically mono-crystal layer directly bonded to a second isolation layer, and said second memory layer comprises a second monolithically mono-crystal layer directly bonded to said second isolation layer, and said first mono-crystal layer is bonded on top of said first isolation layer, and said second memory transistor is self-aligned to said first memory transistor. - View Dependent Claims (9, 10, 11, 12)
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13. A 3D memory device, comprising:
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a first memory layer comprising a first memory transistor with side gates; a second memory layer comprising a second memory transistor with side gates; wherein said first memory layer comprises a first monolithically mono-crystal layer and a first isolation layer, and said second memory layer comprises a second monolithically mono-crystal layer directly bonded to said first isolation layer, said second memory layer is covered by a second isolation layer, and said second memory transistor is self-aligned to said first memory transistor; a periphery circuits layer comprising logic transistors used for controlling said memory is bonded on top of said second isolation layer. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification