Package comprising an electrical circuit

• US 8,581,357 B2
• Filed: 04/24/2007
• Issued: 11/12/2013
• Est. Priority Date: 04/25/2006
• Status: Active Grant

• Current Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: Vogt, Holger, Bauer, Jochen
• Primary Examiner(s): Tran, Tony
• Application Number:
  US12/298,320
• Publication Number:
  US 20090102003A1
• Time in Patent Office: 2,394 Days
• Field of Search: 438/50, 438/64, 438/52, 438/E21.613, 257/433, 257/E21.499, 257/E31.11
• US Class Current: 257/433
• CPC Class Codes: B81B 2201/0278 Temperature sensors
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: G01J 5/02 Constructional details
• CPC Class Codes: G01J 5/023 Particular leg structure or construction or shape; Nanotubes
• CPC Class Codes: G01J 5/04 Casings
• CPC Class Codes: G01J 5/045 Sealings; Vacuum enclosures; Encapsulated packages; Wafer bonding structures; Getter arrangements getter arrangements per se H01L23/26 and H01L21/3221
• CPC Class Codes: G01J 5/046 Materials; Selection of thermal materials
• CPC Class Codes: G01J 5/0875 Windows; Arrangements for fastening thereof
• CPC Class Codes: G01J 5/20 using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14649 Infrared imagers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A package including an electrical circuit may be produced in a more efficient manner when on a substrate including a plurality of electrical circuits the circuits are tested for their functionality and when the functional circuits are connected, by means of a frame enclosing the circuit on the surface of the substrate, to a second substrate whose surface area is smaller than that of the first substrate. The substrates are connected, by means of a second frame, which is adapted to the first frame and is located on the surface of the second substrate, such that the first and second frames lie one on top of the other. Subsequently, the functional packaged circuits may be singulated in a technologically simple manner.

Claims

1. A method of producing a plurality of packages each comprising an electrical circuit, the method comprising:

providing a wafer comprising a plurality of electrical circuits;

testing the plurality of electrical circuits for their functionality so as to obtain an identification of functional electrical circuits and dysfunctional electrical circuits among the plurality of electrical circuits;

selecting a subset of the plurality of electrical circuits, the subset including at least one of the functional electrical circuits, according to the identification of functional electrical circuits and dysfunctional electrical circuits;

respectively producing, for the subset of the plurality of electrical circuits, a first frame, which encloses the at least one functional electrical circuit, on a surface of the wafer;

individually connecting, by use of a flip-chip bonder, and for the subset of the plurality of electrical circuits, a lid comprising a second frame, which is adapted to the first frame, on a surface of the lid, to the wafer so that the first frame and the second frame lie on top of each other so as to package the at least one functional electrical circuit, wherein the step of individually connecting is not performed on, and leaves unpackaged, any electrical circuit of the plurality of electrical circuits not included in the subset of the plurality of electrical circuits; and

singulating the plurality of electrical circuits by separating the wafer along singulation lines which do not intersect any of circumferences of the lids so as to yield a plurality of packages comprising the functional electrical circuits;

wherein

the step of respectively producing the first frame includes;

producing a first frame portion from a first metal; and

producing a second frame portion from a second metal on the first frame portion, the first and second metals selected such that a first melting temperature of an alloy formed from the first and second metals is higher than a second melting temperature of the second metal.

2. The method as claimed in claim 1, wherein the plurality of electrical circuits comprise bolometers.

3. The method as claimed in claim 1, wherein individually connecting comprises interconnecting, for the subset of electrical circuits, the lid and the wafer in a gas-tight manner.

4. The method as claimed in claim 1, wherein the individually connecting is performed in a vacuum or in a protective-gas atmosphere.

5. The method as claimed in claim 1,

wherein the individually connecting comprises connecting, for the subset of electrical circuits, the second frame such that a side of the second frame facing the wafer comprises the first metal.

6. The method as claimed in claim 5, wherein the first metal is copper and the second metal is tin.

7. The method as claimed in claim 5, wherein the first melting temperature is higher than 400°

C., and wherein the second melting temperature is lower than 350°

C.

8. The method as claimed in claim 1, wherein the respectively producing the first frame portion comprises producing a diffusion layer from a metallic material.

9. The method as claimed in claim 8, wherein the diffusion layer comprises a combination of one or several layers of the following materials:

Ti, TiN, TiW.

10. The method as claimed in claim 1, wherein the respectively producing the first frame comprises depositing an electrical solder melting at a predetermined temperature on a side of the frame which faces away from the surface of the lid.

11. The method as claimed claim 1, wherein the individually connecting comprises:

heating the wafer and the lids for a first time period so as to create a preliminary connection;

following the first time span, transporting the preliminarily connected wafer and lids to a heatable process chamber; and

heating the wafer and the lids for a second time span within the heatable process chamber so as to create a final connection.

12. The method as claimed in claim 1, wherein in the step of providing the wafer, the plurality of electrical circuits are integrated within the wafer.

13. The method as claimed in claim 1, wherein the lids are at least partly transmissive to wavelengths in the infrared spectral range.

14. The method as claimed in claim 1, wherein the lid comprises an integrated circuit.

15. The method as claimed in claim 1, wherein the step of individually connecting the lid to the wafer is performed by means of a solid liquid interdiffusion method, wherein the connecting additionally comprises:

coating at least one of the first frame and the second frame with an adhesive; and

preliminarily connecting the first and second frames by means of the adhesive so as to achieve relative mutual fixing of the wafer and the lids, wherein the adhesive is selected such that same evaporates during the solid liquid interdiffusion method.

16. The method as claimed in claim 15, wherein the adhesive is bibenzyl, ethylene glycol or wax.

17. The method according to claim 1, the further comprising:

providing a further wafer;

producing, for the subset of the plurality of electrical circuits, the second frame on the further wafer; and

dicing the further wafer so as to singulate the second frames and obtain the lids.

18. The method according to claim 17, wherein the producing, for the subset of the plurality of electrical circuits, the second frame on the further wafer comprises depositing material of the second frame onto the further wafer.