Hybrid integrated circuit device and electronic device

• US 8,581,395 B2
• Filed: 06/14/2012
• Issued: 11/12/2013
• Est. Priority Date: 02/06/2001
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Moriyama, Shinji, Yamada, Tomio
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US13/523,464
• Publication Number:
  US 20120248630A1
• Time in Patent Office: 516 Days
• Field of Search: 257/678, 257/724, 257/774, 257/784, 257/787, 257/E23.011, 257/E23.067, 257/E23.116, 257/E23.129
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H03G 3/3042 : in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H05K 1/0263 : High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board H05K1/0293 takes precedence
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/183 : Components mounted in and supported by recessed areas of the printed circuit board
• CPC Class Codes: H05K 2201/099 : Coating over pads, e.g. solder resist partly over pads
• CPC Class Codes: H05K 2201/09909 : Special local insulating pattern, e.g. as dam around component
• CPC Class Codes: H05K 2201/10371 : Shields or metal cases
• CPC Class Codes: H05K 3/3405 : Edge mounted components, e.g. terminals
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/3452 : Solder masks

Abstract

A hybrid integrated circuit device having high mount reliability includes a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include ones which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

Claims

1. An electronic device comprising:

a) a wiring substrate having a first main surface, a second main surface opposite the first main surface, a plurality of pads formed over the first main surface, a conductive layer formed over the second main surface, and an insulating layer formed over the second main surface;

b) a semiconductor chip mounted over the first main surface of the wiring substrate and being electrically connected to a first pad of the plurality of the pads;

c) a passive component mounted over the first main surface of the wiring substrate and being electrically connected to a second pad of the plurality of the pads; and

d) a sealing body sealing the semiconductor chip and the passive component,

wherein the insulating layer is formed to partially cover the conductive layer and has a plurality of first openings to provide a plurality of first conductive patterns formed of the conductive layer and a plurality of second openings to provide a plurality of second conductive patterns formed of the conductive layer,

wherein the plurality of second conductive patterns are arranged to surround the plurality of first conductive patterns in a plan view,

wherein the plurality of first conductive patterns are arranged in a matrix formation in the plan view, and

wherein an each area of the plurality of first conductive patterns is larger than an each area of the plurality of second conductive patterns.

2. The electronic device according to claim 1,

wherein each of the plurality first and second conductive patterns exposed from the plurality of first and second openings of the insulating layer is a pattern which can be soldered.

3. The electronic device according to claim 1,

wherein the plurality of first conductive patterns are patterns to which a ground potential is supplied from an outside.

4. The electronic device according to claim 1,

wherein the insulating layer is comprised of a solder resist.

5. The electronic device according to claim 1,

wherein the sealing body is a cap made of metal.

6. The electronic device according to claim 1,

wherein the plurality of first conductive pattern have a pattern electrically connected to the first pad via a plurality of through holes.

7. The electronic device according to claim 6,

wherein a bottom surface of the semiconductor chip is electrically connected to the first pad via a conductive adhesive.

8. The electronic device according to claim 1,

wherein the plurality of second conductive patterns are arranged along sides of the wiring substrate.

9. The electronic device according to claim 8,

wherein the plurality of second conductive patterns are arranged by one row.

10. The electronic device according to claim 1,

wherein each shape of the plurality of first and second conductive patterns is substantially rectangular shape in the plan view.

11. The electronic device according to claim 1,

wherein the plurality of passive components includes chip resistor and chip condenser.

12. The electronic device according to claim 1,

wherein the semiconductor chip is electrically connected to the wiring substrate via a plurality of metal wires.

13. The electronic device according to claim 1,

wherein a space between each of the plurality of the first conductive patterns is larger than a space between each of the plurality of the second conductive patterns.

14. The electronic device according to claim 1,

wherein a distance between centers of each of the plurality of first conductive patterns is longer than a distance between centers of each of the plurality of second conductive patterns.

15. An electronic device comprising:

a) a wiring substrate having a first main surface, a second main surface opposite the first main surface, a plurality of pads formed over the first main surface, a conductive layer formed over the second main surface, and an insulating layer formed over the second main surface;

b) a semiconductor chip mounted over one surface of the wiring substrate that is connected to a first one of the pads; and

c) a sealing body sealing the semiconductor chip,

wherein the insulating layer is formed to partially cover the conductive layer and has a plurality of first openings to provide a plurality of first electrodes formed of the conductive layer and a plurality of second openings to provide a plurality of second electrodes formed of the conductive layer,

wherein the plurality of second electrodes are arranged to surround the plurality of first electrodes in a plan view,

wherein the plurality of first electrodes are arranged in a matrix formation in the plan view, and

wherein an each area of the plurality of first electrodes is larger than an each area of the plurality of second electrodes.

16. The electronic device according to claim 15, further comprising:

a passive component mounted over a the first main surface of the wiring substrate and being electrically connected to a second pad of the plurality of the pads.

17. An electronic device comprising:

a wiring substrate having a plurality of pads formed over one surface, and a conductive layer and an insulating layer formed over an opposite surface;

a semiconductor chip mounted over the one surface and being electrically connected to a first one of the plurality of pads; and

a sealing layer covering at least the semiconductor chip,

a plurality of first areas of the conductive layer exposed from the insulating layer and a plurality of second areas of the conductive layer exposed from the insulating layer, providing first and second electrodes,

wherein the plurality of second electrodes surround the plurality of first electrodes and the plurality of first electrodes are laid out across the opposite surface of the wiring substrate, and

wherein an area of each of the plurality of first electrodes is larger than an area of each of the plurality of second electrodes.

18. The electronic device according to claim 17, further comprising:

a passive component mounted over the one surface of the wiring substrate and being electrically connected to a second one of the plurality of pads.