Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures

• US 8,581,404 B2
• Filed: 10/31/2008
• Issued: 11/12/2013
• Est. Priority Date: 07/09/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megit Acquisition Corp.
• Inventors: Chou, Chiu-Ming, Lin, Mou-Shiung
• Primary Examiner(s): Roman, Angel
• Application Number:
  US12/262,195
• Publication Number:
  US 20090057894A1
• Time in Patent Office: 1,838 Days
• Field of Search: 257/750, 257/758, 257/E23.153
• US Class Current: 257/750
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A method for fabricating multiple metal layers includes the following steps. An electronic component is provided with multiple contact points. A first metal layer is deposited over said electronic component. A first mask layer is deposited over said first metal layer. A second metal layer is deposited over said first metal layer exposed by an opening in said first mask layer. Said first mask layer is removed. A second mask layer is deposited over said second metal layer. A third metal layer is deposited over said second metal layer exposed by an opening in said second mask layer. Said second mask layer is removed. Said first metal layer not covered by said second metal layer is removed.

Claims

1. An integrated circuit die comprising:

a semiconductor substrate;

multiple electronic devices in and on said semiconductor substrate;

an interconnection structure over said semiconductor substrate, wherein said interconnection structure comprises a first interconnection layer and a second interconnection layer over said first interconnection layer;

a passivation layer over said interconnection structure, wherein a first opening in said passivation layer is over a first contact point of said interconnection structure, and said first contact point is at a bottom of said first opening, wherein a second opening in said passivation layer is over a second contact point of said interconnection structure, and said second contact point is at a bottom of said second opening, wherein a third opening in said passivation layer is over a third contact point of said interconnection structure, and said third contact point is at a bottom of said third opening, and wherein a fourth opening in said passivation layer is over a fourth contact point of said interconnection structure, and said fourth contact point is at a bottom of said fourth opening;

a third interconnection layer on said passivation layer and on said first, second, third and fourth contact points, wherein said first, second, third and fourth contact points are connected to one another through said third interconnection layer, wherein said third interconnection layer has a thickness greater than that of said first interconnection layer and that of said second interconnection layer, respectively, wherein said third interconnection layer comprises a bottom layer on said passivation layer and on said first, second, third and fourth contact points, and a first plated metal layer on said bottom layer, wherein said bottom layer comprises an adhesion layer and a seed layer;

a first metal bump on said third interconnection layer and over said first plated metal layer, wherein said first metal bump has a thickness greater than that of said third interconnection layer, and wherein said first metal bump is connected to said first, second, third and fourth contact points through said third interconnection layer; and

a second metal bump on said third interconnection layer and over said first plated metal layer, wherein said second metal bump has a thickness greater than that of said third interconnection layer, wherein said second metal bump is connected to said first, second, third and fourth contact points through said third interconnection layer, wherein said second metal bump is connected to said first metal bump through said third interconnection layer, and wherein said first and second metal bumps are provided by a metal layer comprising a second plated metal layer over said first plated metal layer.

2. The integrated circuit die of claim 1, wherein said first plated metal layer comprises gold.

3. The integrated circuit die of claim 1, wherein said second plated metal layer comprises gold.

4. The integrated circuit die of claim 1, wherein said third interconnection layer comprises a ground bus on said passivation layer and on said first, second, third and fourth contact points, wherein said first, second, third and fourth contact points are connected to one another through said ground bus, wherein said first metal bump is connected to said first, second, third and fourth contact points through said ground bus, and wherein said second metal bump is connected to said first, second, third and fourth contact points through said ground bus.

5. The integrated circuit die of claim 1, wherein said third interconnection layer comprises a power bus on said passivation layer and on said first, second, third and fourth contact points, wherein said first, second, third and fourth contact points are connected to one another through said power bus, wherein said first metal bump is connected to said first, second, third and fourth contact points through said power bus, and wherein said second metal bump is connected to said first, second, third and fourth contact points through said power bus.

6. The integrated circuit die of claim 1, wherein said first metal bump is further over said first contact point.

7. The integrated circuit die of claim 1, wherein said first metal bump is further over said first contact point, and said second metal bump is further over said second contact point.

8. An integrated circuit die comprising:

a semiconductor substrate;

multiple electronic devices in and on said semiconductor substrate;

an interconnection structure over said semiconductor substrate, wherein said interconnection structure comprises a first interconnection layer and a second interconnection layer over said first interconnection layer;

a passivation layer over said interconnection structure, wherein a first opening in said passivation layer is over a first contact point of said interconnection structure, and said first contact point is at a bottom of said first opening, wherein a second opening in said passivation layer is over a second contact point of said interconnection structure, and said second contact point is at a bottom of said second opening, wherein a third opening in said passivation layer is over a third contact point of said interconnection structure, and said third contact point is at a bottom of said third opening, and wherein a fourth opening in said passivation layer is over a fourth contact point of said interconnection structure, and said fourth contact point is at a bottom of said fourth opening;

a third interconnection layer on said passivation layer and on said first, second, third and fourth contact points, wherein said first, second, third and fourth contact points are connected to one another through said third interconnection layer, wherein said third interconnection layer has a thickness greater than that of said first interconnection layer and that of said second interconnection layer, respectively, wherein said third interconnection layer comprises a bottom layer on said passivation layer and on said first, second, third and fourth contact points, and a plated metal layer on said bottom layer, wherein said bottom layer comprises an adhesion layer and a seed layer;

a first metal bump on said third interconnection layer and over said plated metal layer, wherein said first metal bump has a thickness greater than that of said third interconnection layer, wherein said first metal bump is connected to said first, second, third and fourth contact points through said third interconnection layer, and wherein said first metal bump comprises gold at a top of said first metal bump; and

a second metal bump on said third interconnection layer and over said plated metal layer, wherein said second metal bump has a thickness greater than that of said third interconnection layer, wherein said second metal bump is connected to said first, second, third and fourth contact points through said third interconnection layer, wherein said second metal bump is connected to said first metal bump through said third interconnection layer, and wherein said second metal bump comprises gold at a top of said second metal bump.

9. The integrated circuit die of claim 8, wherein said plated metal layer comprises gold.

10. The integrated circuit die of claim 8, wherein said third interconnection layer comprises a ground bus on said passivation layer and on said first, second, third and fourth contact points, wherein said first, second, third and fourth contact points are connected to one another through said ground bus, wherein said first metal bump is connected to said first, second, third and fourth contact points through said ground bus, and wherein said second metal bump is connected to said first, second, third and fourth contact points through said ground bus.

11. The integrated circuit die of claim 8, wherein said third interconnection layer comprises a power bus on said passivation layer and on said first, second, third and fourth contact points, wherein said first, second, third and fourth contact points are connected to one another through said power bus, wherein said first metal bump is connected to said first, second, third and fourth contact points through said power bus, and wherein said second metal bump is connected to said first, second, third and fourth contact points through said power bus.

12. The integrated circuit die of claim 8, wherein said first metal bump is further over said first contact point.

13. The integrated circuit die of claim 8, wherein said first metal bump is further over said first contact point, and said second metal bump is further over said second contact point.

14. The integrated circuit die of claim 8, wherein said first metal bump is not vertically over said first contact point, said second contact point and said third contact point.

15. An integrated circuit die comprising:

a semiconductor substrate;

multiple electronic devices in and on said semiconductor substrate;

an interconnection structure over said semiconductor substrate, wherein said interconnection structure comprises a first interconnection layer and a second interconnection layer over said first interconnection layer;

a passivation layer over said interconnection structure, wherein a first opening in said passivation layer is over a first contact point of said interconnection structure, and said first contact point is at a bottom of said first opening, wherein a second opening in said passivation layer is over a second contact point of said interconnection structure, and said second contact point is at a bottom of said second opening, wherein a third opening in said passivation layer is over a third contact point of said interconnection structure, and said third contact point is at a bottom of said third opening, and wherein a fourth opening in said passivation layer is over a fourth contact point of said interconnection structure, and said fourth contact point is at a bottom of said fourth opening;

a ground bus on said passivation layer and on said first, second, third and fourth contact points, wherein said first, second, third and fourth contact points are connected to one another through said ground bus, wherein said ground bus has a thickness greater than that of said first interconnection layer and that of said second interconnection layer, respectively, wherein said ground bus comprises a bottom layer on said passivation layer and on said first, second, third and fourth contact points, and a first plated metal layer on said bottom layer, wherein said bottom layer comprises an adhesion layer and a seed layer;

a first metal bump on said ground bus and over said first plated metal layer, wherein said first metal bump has a thickness greater than that of said ground bus, and wherein said first metal bump is connected to said first, second, third and fourth contact points through said ground bus; and

a second metal bump on said ground bus and over said first plated metal layer, wherein said second metal bump has a thickness greater than that of said ground bus, wherein said second metal bump is connected to said first, second, third and fourth contact points through said ground bus, wherein said second metal bump is connected to said first metal bump through said ground bus, and wherein said first and second metal bumps are provided by a metal layer comprising a second plated metal layer over said first plated metal layer.

16. The integrated circuit die of claim 15, wherein said first plated metal layer comprises gold.

17. The integrated circuit die of claim 15, wherein said second plated metal layer comprises gold.

18. The integrated circuit die of claim 15, wherein said first metal bump is further over said first contact point.

19. The integrated circuit die of claim 15, wherein said first metal bump is further over said first contact point, and said second metal bump is further over said second contact point.

20. The integrated circuit die of claim 15, wherein said first metal bump is not vertically over said first contact point, said second contact point and said third contact point.

21. An integrated circuit die comprising:

a semiconductor substrate;

multiple electronic devices in and on said semiconductor substrate;

an interconnection structure over said semiconductor substrate, wherein said interconnection structure comprises a first interconnection layer and a second interconnection layer over said first interconnection layer;

a passivation layer over said interconnection structure, wherein a first opening in said passivation layer is over a first contact point of said interconnection structure, and said first contact point is at a bottom of said first opening, wherein a second opening in said passivation layer is over a second contact point of said interconnection structure, and said second contact point is at a bottom of said second opening, wherein a third opening in said passivation layer is over a third contact point of said interconnection structure, and said third contact point is at a bottom of said third opening, and wherein a fourth opening in said passivation layer is over a fourth contact point of said interconnection structure, and said fourth contact point is at a bottom of said fourth opening;

a first interconnect on said passivation layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said first interconnect;

a second interconnect on said passivation layer and on said third and fourth contact points, wherein a gap is between said first and second interconnects, wherein said third contact point is connected to said fourth contact point through said second interconnect, wherein said first and second interconnects are provided by a circuit layer comprising a bottom layer on said passivation layer and on said first, second, third and fourth contact points, and a first plated metal layer on said bottom layer, wherein said bottom layer comprises an adhesion layer and a seed layer; and

a metal bump on said first interconnect, vertically over said first contact point and over said first plated metal layer, wherein said metal bump has a thickness greater than that of said first interconnect, wherein said metal bump is connected to said first and second contact points through said first interconnect, wherein said metal bump comprises a second plated metal layer over said first plated metal layer, wherein there is no metal bump on said second interconnect.

22. The integrated circuit die of claim 21, wherein said first plated metal layer comprises gold.

23. The integrated circuit die of claim 21, wherein said second plated metal layer comprises gold.