Semiconductor device and method for manufacturing the same

• US 8,581,413 B2
• Filed: 06/24/2011
• Issued: 11/12/2013
• Est. Priority Date: 03/26/2007
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sasagawa, Shinya
• Primary Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US13/167,765
• Publication Number:
  US 20110248345A1
• Time in Patent Office: 872 Days
• Field of Search: 257210-211, 257/503, 257/508, 257E33062-E33066, 257E31124-E31126, 257/E51.019
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for easily manufacturing a semiconductor device in which variation in thickness or disconnection of a source electrode or a drain electrode is prevented is proposed. A semiconductor device includes a semiconductor layer formed over an insulating substrate; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; an opening which reaches the semiconductor layer and is formed at least in the first insulating layer and the second insulating layer; and a step portion formed at a side surface of the second insulating layer in the opening.

Claims

1. A semiconductor device comprising:

a first insulating layer over a substrate;

a transistor comprising a source region and a drain region over the first insulating layer;

a second insulating layer over the source region and the drain region;

a third insulating layer over the second insulating layer;

a contact hole reaching the first insulating layer and in the source region or the drain region, the second insulating layer, and the third insulating layer; and

a conductive layer over the second insulating layer, the conductive layer covering a side surface of the contact hole, and being in contact with the first insulating layer,

wherein an opening in the source region or the drain region is smaller than an opening in the second insulating layer, and the opening in the second insulating layer is smaller than an opening in the third insulating layer.

2. The semiconductor device according to claim 1, wherein a thickness of the source region and the drain region is 10 to 30 nm.

3. The semiconductor device according to claim 1, wherein the third insulating layer comprises one selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride oxide, an organic material, a siloxane material, and an oxazole resin.

4. The semiconductor device according to claim 1, further comprising a gate electrode with the second insulating layer between the gate electrode, and the source region and the drain region.

5. The semiconductor device according to claim 4, wherein the gate electrode comprises one selected from the group consisting of tantalum, tungsten, titanium, molybdenum, aluminum, copper, chromium, and niobium.

6. The semiconductor device according to claim 4, wherein an insulating sidewall is provided at a side surface of the gate electrode.

7. The semiconductor device according to claim 6, wherein a thickness of the source region and the drain region is 10 to 30 nm.

8. The semiconductor device according to claim 6, wherein the third insulating layer comprises one selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride oxide, an organic material, a siloxane material, and an oxazole resin.

9. The semiconductor device according to claim 6, wherein the gate electrode comprises one selected from the group consisting of tantalum, tungsten, titanium, molybdenum, aluminum, copper, chromium, and niobium.

10. A semiconductor device comprising:

a first insulating layer over a substrate;

a transistor comprising a source region and a drain region over the first insulating layer;

a second insulating layer over the source region and the drain region;

a third insulating layer over the second insulating layer;

a contact hole reaching the first insulating layer and in the source region or the drain region, the second insulating layer, and the third insulating layer; and

a conductive layer over the second insulating layer, the conductive layer covering a side surface of the contact hole, and being in contact with the first insulating layer,

wherein a silicide region is provided in the source region and the drain region,

wherein the conductive layer is in contact with the silicide region, and

wherein an opening in the source region or the drain region is smaller than an opening in the second insulating layer, and the opening in the second insulating layer is smaller than an opening in the third insulating layer.

11. The semiconductor device according to claim 10, wherein a thickness of the source region and the drain region is 10 to 30 nm.

12. The semiconductor device according to claim 10, wherein the third insulating layer comprises one selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride oxide, an organic material, a siloxane material, and an oxazole resin.

13. The semiconductor device according to claim 10, further comprising a gate electrode with the second insulating layer between the gate electrode, and the source region and the drain region.

14. The semiconductor device according to claim 13, wherein the gate electrode comprises one selected from the group consisting of tantalum, tungsten, titanium, molybdenum, aluminum, copper, chromium, and niobium.

15. The semiconductor device according to claim 10, wherein the silicide region comprises one selected from the group consisting of nickel, titanium, cobalt, and platinum.

16. The semiconductor device according to claim 13, wherein an insulating sidewall is provided at a side surface of the gate electrode.

17. The semiconductor device according to claim 16, wherein a thickness of the source region and the drain region is 10 to 30 nm.

18. The semiconductor device according to claim 16, wherein the third insulating layer comprises one selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride oxide, an organic material, a siloxane material, and an oxazole resin.

19. The semiconductor device according to claim 16, wherein the gate electrode comprises one selected from the group consisting of tantalum, tungsten, titanium, molybdenum, aluminum, copper, chromium, and niobium.

20. The semiconductor device according to claim 16, wherein the silicide region comprises one selected from the group consisting of nickel, titanium, cobalt, and platinum.