Circuit and method for generating PWM signal for DC-DC converter using dimming signal and LED driving circuit for backlight having the same

• US 8,581,511 B2
• Filed: 02/09/2011
• Issued: 11/12/2013
• Est. Priority Date: 03/18/2010
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Kim, Eung-suen, Han, Jin-sub, Baik, Seung-beom, Lim, Chang-sik
• Primary Examiner(s): TRAN, THUY V
• Application Number:
  US13/023,580
• Publication Number:
  US 20110227502A1
• Time in Patent Office: 1,007 Days
• Field of Search: 345/82, 345/102, 315/291, 315/307, 315/308, 315/DIG.4
• US Class Current: 315/291
• CPC Class Codes: G09G 3/34 by control of light from an independent source

Abstract

A pulse width modulation (PWM) signal generating circuit that generates a PWM signal for a DC-DC converter using a dimming signal is provided. The PWM signal generating circuit includes a normal PWM signal generator configured to generate a normal PWM signal based on a clock signal provided to the DC-DC converter, and a compensation PWM signal generator configured to generate a compensation PWM signal based on the clock signal and the dimming signal.

Claims

1. A pulse width modulation (PWM) signal generating circuit configured to generate a PWM signal for a DC-DC converter using a dimming signal, the PWM signal generating circuit comprising:

a normal PWM signal generator configured to generate a normal PWM signal based on a clock signal provided to the DC-DC converter; and

a compensation PWM signal generator configured to generate a compensation PWM signal based on the clock signal and the dimming signal.

2. The PWM signal generating circuit as claimed in claim 1, wherein the normal PWM signal generator is further configured to generate the normal PWM signal during a first level period of the dimming signal.

3. The PWM signal generating circuit as claimed in claim 2, wherein the first level period of the dimming signal comprises a high-level period of the dimming signal.

4. The PWM signal generating circuit as claimed in claim 1, wherein the compensation PWM signal generator is further configured to generate at least one compensation PWM signal during a second level period of the dimming signal.

5. The PWM signal generating circuit as claimed in claim 4, wherein the second level period of the dimming signal comprises a low-level period.

6. The PWM signal generating circuit as claimed in claim 1, wherein the compensation PWM signal has a pulse width that is the same as a pulse width of the normal PWM signal.

7. The PWM signal generating circuit as claimed in claim 6, wherein the compensation PWM signal has a pulse width that is the same as a pulse width of the clock signal.

8. The PWM signal generating circuit as claimed in claim 1, wherein the compensation PWM signal generator comprises:

a signal detector configured to;

detect a low-level period of the dimming signal; and

generate a detection signal; and

a signal generator configured to;

receive the detection signal from the signal detector; and

generate the compensation PWM signal.

9. The PWM signal generating circuit as claimed in claim 8, wherein the signal detector comprises a flip-flop configured to:

detect the low-level period of the dimming signal at a rising edge of the clock signal; and

generate the detection signal.

10. The PWM signal generating circuit as claimed in claim 8, wherein the signal generator comprises a flip-flop configured to:

receive the detection signal from the signal detector; and

generate the compensation PWM signal.

11. The PWM signal generating circuit as claimed in claim 10, wherein the flip-flop of the signal generator is reset at a negative edge of the clock signal.

12. The PWM signal generating circuit as claimed in claim 11, wherein the compensation PWM signal has a pulse width that is the same as a pulse width of the normal PWM signal.

13. The PWM signal generating circuit as claimed in claim 1, further comprising:

an output unit configured to;

receive the normal PWM signal from the normal PWM signal generator and the compensation PWM signal from the compensation PWM signal generator; and

provide the normal PWM signal and the compensation PWM signal to the DC-DC converter.

14. The PWM signal generating circuit as claimed in claim 13, wherein the output unit comprises an adder configured to:

add the normal PWM signal received from the normal PWM signal generator and the compensation PWM signal received from the compensation PWM signal generator; and

provide an added PWM signal to the DC-DC converter as the PWM signal.

15. A light emitting diode (LED) driving circuit for backlight, comprising:

a PWM signal generator configured to generate a PWM signal using a clock signal and a dimming signal;

a DC-DC converter configured to provide an output voltage to an LED of an LED array for backlight, based on the PWM signal generated by the PWM signal generator; and

an LED driving unit configured to generate a driving signal for driving the LED using the dimming signal, wherein;

the PWM signal generator comprises;

a normal PWM signal generator configured to generate a normal PWM signal based on the clock signal during a high-level period of the dimming signal; and

a compensation PWM signal generator configured to generate a compensation PWM signal based on the clock signal during a low-level period of the dimming signal.

16. The LED driving circuit as claimed in claim 15, wherein the compensation PWM signal has a pulse width that is the same as a pulse width of the normal PWM signal.

17. The LED driving circuit as claimed in claim 16, wherein the compensation PWM signal has a pulse width that is the same as a pulse width of the clock signal.

18. The LED driving circuit as claimed in claim 15, wherein the compensation PWM signal generator comprises:

a RS flip-flop configured to;

generate a low-level period of the dimming signal at a rising edge of the clock signal; and

generate a detection signal; and

a D flip-flop configured to generate an output signal at the rising edge of the clock signal based on the detection signal, the D flip-flop being reset at a falling edge of the clock signal to generate the compensation PWM signal.

19. The LED driving circuit as claimed in claim 15, further comprising:

an adder configured to;

add the normal PWM signal received from the normal PWM signal generator and the compensation PWM signal received from the compensation PWM signal generator; and

provide an added PWM signal to the DC-DC converter.

20. A method configured to generate a PWM signal for a DC-DC converter using a dimming signal, the method comprising:

generating a normal PWM signal based on a clock signal during a first period of a dimming signal;

providing the normal PWM signal to the DC-DC converter; and

generating a compensation PWM signal based on the clock signal during a second period of the dimming signal.

21. The method as claimed in claim 20, wherein the generating of the normal PWM signal comprises generating the normal PWM signal during a high-level period of the dimming signal.

22. The method as claimed in claim 20, wherein the generating of the compensation PWM signal comprises generating the compensation PWM signal during a low-level period of the dimming signal.

23. The method as claimed in claim 20, wherein the compensation PWM signal has a pulse width that is the same as a pulse width of the normal PWM signal.