Integrated circuits with multi-stage logic regions

• US 8,581,624 B2
• Filed: 03/29/2012
• Issued: 11/12/2013
• Est. Priority Date: 03/29/2012
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Cashman, David, Lewis, David, Manohararajah, Valavan
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US13/434,847
• Publication Number:
  US 20130257476A1
• Time in Patent Office: 593 Days
• Field of Search: 326 37- 41
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A programmable logic region on a programmable integrated circuit may include a first set of look-up tables that receive programmable logic region input signals and a second set of look-up tables that produce programmable logic region output signals. Multiplexer circuitry may be interposed between the first and second sets of look-up tables. The multiplexer circuitry may receive the programmable logic region input signals in parallel with the output signals from the first set of look-up tables and may provide corresponding selected signals to the second set of look-up tables. The programmable logic region input signals may be shared by the first and second sets of look-up tables. Logic circuitry may be coupled to outputs of the first and second sets of look-up tables. The logic circuitry may be configured to logically combine output signals from the first and second sets of look-up tables.

Claims

1. A programmable logic region on a programmable integrated circuit, comprising:

a first set of look-up tables operable to receive programmable logic region input signals for the programmable logic region;

a second set of look-up tables operable to provide programmable logic region output signals for the programmable logic region;

multiplexer circuitry coupled between the first set of look-up tables and the second set of look-up tables, wherein the multiplexer circuitry is operable to receive the programmable logic region input signals and output signals from the first set of look-up tables and is further operable to provide corresponding selected signals to the second set of look-up tables; and

a plurality of inputs at which the programmable logic region input signals are received by the programmable logic region, wherein at least one input of the plurality of inputs is coupled in parallel to the first and second sets of look-up tables.

2. The programmable logic region defined in claim 1 further comprising:

a programmable element operable to provide a static output signal that configures the multiplexer circuitry so that the first and second sets of look-up tables form a cascade configuration in which the output signals from the first set of look-up tables are provided to the second set of look-up tables.

3. The programmable logic region defined in claim 1 further comprising logic circuitry coupled to the first and second set of look-up tables, wherein the logic circuitry is operable to pass the programmable logic region output signals to outputs of the programmable logic region in a first configuration and is further operable to modify the programmable logic region output signals based on the output signals from the first set of look-up tables in a second configuration.

4. The programmable logic region defined in claim 3 wherein the logic circuitry comprises:

a logic AND gate coupled to the first and second sets of look-up tables; and

a logic OR gate interposed between the logic AND gate and the second set of look-up tables.

5. The programmable logic region defined in claim 3 wherein the logic circuitry comprises:

a multiplexing circuit coupled to the first and second sets of look-up tables; and

a logic OR gate interposed between the multiplexing circuit and the second set of look-up tables, wherein the logic OR gate is coupled to a control input of the multiplexing circuit.

6. The programmable logic region defined in claim 3 further comprising a delay element coupled to the logic circuitry, wherein the delay element forms a feedback path between the logic circuitry and the first set of look-up tables.

7. A programmable logic region on a programmable integrated circuit, said programmable logic region comprising:

a first set of look-up tables operable to receive programmable logic region input signals for the programmable logic region;

a second set of look-up tables operable to provide programmable logic region output signals for the programmable logic region; and

multiplexer circuitry coupled between the first set of look-up tables and the second set of look-up tables, wherein the multiplexer circuitry is operable to receive output signals from at least two different look-up tables of the first set of look-up tables and is configured to route one of the output signals from the two different look-up tables to a given look-up table of the second set of look-up tables, and wherein the first set of look-up tables is further operable to provide additional programmable logic region output signals for the programmable logic region.

8. The programmable logic region defined in claim 7 wherein the multiplexer circuitry comprises a plurality of multiplexer circuits each operable to receive at least one input signal of the programmable logic region input signals in parallel with at least one output signal of the output signals from the first set of look-up tables.

9. The programmable logic region defined in claim 8 wherein each multiplexer circuit of the plurality of multiplexer circuits is coupled to a respective programmable memory element that is operable to produce a static output signal that configures that multiplexer circuit to route a selected signal from the at least one input signal of the programmable logic region input signals and the at least one of the output signals of that multiplexer to the second set of look-up tables.

12. The programmable logic region defined in claim 7 wherein at least one look-up table of the first set of look-up tables is operable to receive a carry input signal and to produce a first carry output signal and a first sum signal based at least partly on the carry input signal, the programmable logic region further comprising:

a routing path between the at least one look-up table of the first set of look-up tables and the given look-up table of the second set of look-up tables, wherein the routing path bypasses the multiplexer circuitry and wherein the given look-up table of the second set of look-up tables is operable to receive the first carry output signal from the first set of look-up tables over the routing path and is further operable to produce a second carry output signal and a second sum signal based at least partly on the first carry output signal.

13. The programmable logic region defined in claim 7 wherein the second set of look-up tables is operable to receive at least one of the programmable logic region input signals.

10. A programmable logic region on a programmable integrated circuit, said programmable logic region comprising:

a first set of look-up tables operable to receive programmable logic region input signals for the programmable logic region;

a second set of look-up tables operable to provide programmable logic region output signals for the programmable logic region;

multiplexer circuitry coupled between the first set of look-up tables and the second set of look-up tables, wherein the multiplexer circuitry is operable to receive output signals from at least two different look-up tables of the first set of look-up tables and is configured to route one of the output signals from the two different look-up tables to a given look-up table of the second set of look-up tables; and

outputs operable to provide the programmable logic region output signals to interconnects on the programmable integrated circuit, wherein the interconnects are operable to route the programmable logic region output signals throughout the programmable integrated circuit.

11. A programmable logic region on a programmable integrated circuit, said programmable logic region comprising:

a first set of look-up tables operable to receive programmable logic region input signals for the programmable logic region;

a second set of look-up tables operable to provide programmable logic region output signals for the programmable logic region;

multiplexer circuitry coupled between the first set of look-up tables and the second set of look-up tables, wherein the multiplexer circuitry is operable to receive output signals from at least two different look-up tables of the first set of look-up tables and is configured to route one of the output signals from the two different look-up tables to a given look-up table of the second set of look-up tables; and

programmable elements operable to provide static output signals to the multiplexer circuitry that determines which output signal from the two different look-up tables is routed to the given look-up table of the second set of look-up tables.

14. A programmable logic region on a programmable integrated circuit, said programmable logic region comprising:

a first look-up table circuit operable to produce a first output signal;

a second look-up table circuit operable to produce a second output signal;

logic circuitry operable to receive the first output signal and the second output signal, wherein the logic circuitry is further operable in a first configuration in which a programmable logic region output signal for the programmable logic region is generated based on the first and second output signals and in a second configuration in which the programmable logic region output signal is generated based on the first output signal;

a first programmable logic region output operable to receive the programmable logic region output signal from the logic circuitry; and

a second programmable logic region output operable to receive the second output signal from the second look-up table circuit.

15. The programmable logic region defined in claim 14 wherein the logic gate comprises:

a logic OR gate operable to receive the second output signal and a static data output signal from a programmable element and to produce an intermediate signal based on the static data output signal and the second output signal.

16. The programmable logic region defined in claim 15 wherein the logic circuitry further comprises:

a logic AND gate operable to receive the intermediate signal and the first output signal and to produce the programmable logic region output signal.

17. The programmable logic region defined in claim 15 wherein the logic circuitry further comprises:

a multiplexing circuit operable to receive the first output signal and an additional static data output signal from an additional programmable element, wherein the multiplexing circuit is further operable to receive the intermediate signal and to select the programmable logic region output signal from the first output signal and the additional static data output signal based on the intermediate signal.

18. The programmable logic region defined in claim 14 further comprising:

a delay element operable to receive the programmable logic region output signal and provide a delayed output signal to the look-up table circuitry, wherein the look-up table circuitry is configured to generate the programmable logic region output signal based on the delayed output signal.

19. The programmable logic region defined in claim 14 wherein the logic circuitry further comprises:

a logic gate operable to receive the second output signal at a first data input and further operable to receive a static data output signal from a programmable element at a second data input, wherein the logic gate is further operable to produce an intermediate signal based on the static data output signal and the second output signal.