Signal-characteristic determined digital-to-analog converter (DAC) filter stage configuration

• US 8,581,756 B1
• Filed: 09/27/2012
• Issued: 11/12/2013
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Duewer, Bruce, Kamath, Gautham Devendra
• Primary Examiner(s): Nguyen, Khai M
• Application Number:
  US13/628,805
• Time in Patent Office: 411 Days
• Field of Search: 341/61, 341/143
• US Class Current: 341/61
• CPC Class Codes: H03H 17/0223 Computation saving measures; Accelerating measures computations per se G06F
• CPC Class Codes: H03H 17/0294 Variable filters; Programmable filters
• CPC Class Codes: H03H 2017/0245 Measures to reduce power consumption H03H17/0223 takes precedence
• CPC Class Codes: H03M 3/32 with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed
• CPC Class Codes: H03M 3/344 by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
• CPC Class Codes: H03M 3/504 the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC

Abstract

A digital signal processing circuit, such as a digital-to-analog converter (DAC) having multiple cascaded processing stages, some of which are selectably placed in a low-power non-operating state according to a lower-power operating mode of the digital signal processing circuit and are placed in an operating state according to another higher-performance operating mode of the circuit. The output sample rates of the stages differ, so that the sample rate through the cascade changes. A signal characteristic determination block generates an indication of one or both of an amplitude and/or frequency of the input signal, so that the operating mode of the digital signal processing circuit is selected in conformity with the indication of amplitude and/or frequency of the input signal.

Claims

1. A reconfigurable signal processing circuit for processing an input signal, comprising:

a detector for generating a measure of at least one of an amplitude or a frequency of the input signal;

a plurality of digital processing stages connected in cascade for processing the input signal, wherein the plurality of processing stages have differing output sample rates while operational; and

a power management block for receiving the measure generated by the detector and determining particular ones of the plurality of digital signal processing stages that are placed in a low-power non-operational state in conformity with the measure of amplitude or frequency, whereby in at least one operating mode, when the measure indicates that the amplitude of the input signal or the frequency of the input signal is below a threshold value, at least one but not all of the plurality of digital signal processing stages is placed in the low-power non-operational state, and wherein when the measure indicates that the amplitude of the input signal or the frequency of the input signal is above the threshold value, the at least one digital signal processing stage is placed in an operational state to provide a higher performance from the plurality of digital signal processing stages.

2. The reconfigurable signal processing circuit of claim 1, wherein the plurality of digital signal processing stages implements at least one filter, and wherein the threshold value is predetermined such that an absolute image amplitude limit is enforced by permitting the at least one filter to have a lower amount of attenuation when the at least one of an amplitude or a frequency of the input signal is below the threshold value.

3. The reconfigurable signal processing circuit of claim 1, wherein the plurality of digital signal processing stages comprises a plurality of interpolators coupled in cascade.

4. The reconfigurable signal processing circuit of claim 3, wherein the plurality of digital signal processing stages comprises a sample rate converter that receives an input from an output of the plurality of interpolators.

5. The reconfigurable signal processing circuit of claim 4, wherein the detector further determines whether the input signal is constant from the measure, and wherein the power management block further disables the sample rate converter when the detector determines that the input signal is constant.

6. The reconfigurable signal processing circuit of claim 1, wherein the detector generates a first measure of the frequency of the input signal and a second measure of the amplitude of the input signal.

7. The reconfigurable signal processing circuit of claim 1, wherein the detector generates a first measure of the frequency of the input signal from a count of zero-crossings of the input signal.

8. The reconfigurable signal processing circuit of claim 1, wherein the reconfigurable signal processing circuit is a digital-to-analog converter.

9. A method of processing an input signal, comprising:

generating a measure of at least one of an amplitude or a frequency of the input signal;

operating a plurality of digital signal processing stages connected in cascade for processing the input signal at differing output sample rates; and

power managing the plurality of digital signal processing stages in conformity with the measure generated by generating by determining particular ones of the plurality of digital signal processing stages to be placed in a low-power non-operational state, whereby in at least one operating mode, when the measure indicates that the amplitude of the input signal or the frequency of the input signal is below a threshold value, at least one but not all of the plurality of digital signal processing stages is placed in the low-power non-operational state, and wherein when the measure indicates that the amplitude of the input signal or the frequency of the input signal is above the threshold value, the at least one digital signal processing stage is placed in an operational state to provide a higher performance from the plurality of digital signal processing stages.

10. The method of claim 9, wherein the providing a plurality of digital signal processing stages provides at least one filter within the cascade of digital signal processing stages, and wherein the threshold value is predetermined such that an absolute image amplitude limit is enforced by permitting the at least one filter to have a lower amount of attenuation when the at least one of an amplitude or a frequency of the input signal is below the threshold value.

11. The method of claim 9, wherein the providing a plurality of digital signal processing stages provides a plurality of interpolators coupled in cascade.

12. The method of claim 11, wherein the plurality of digital signal processing stages comprises a sample rate converter that receives an input from an output of the plurality of interpolators.

13. The method of claim 12, wherein the generating further comprises determining whether the input signal is constant from the measure, and wherein the power managing further disables the sample rate converter when the determining determines that the input signal is constant.

14. The method of claim 9, wherein the generating generates a first measure of the frequency of the input signal and a second measure of the amplitude of the input signal.

15. The method of claim 9, wherein the generating generates a first measure of the frequency of the input signal from a count of zero-crossings of the input signal.

16. The method of claim 9, wherein the plurality of digital signal processing stages are stages of a digital-to-analog converter.

17. An integrated circuit, comprising:

a detector for generating a measure of at least one of an amplitude or a frequency of an input signal;

a plurality of digital processing stages connected in cascade for processing the input signal, wherein the plurality of processing stages have differing output sample rates while operational; and

a power management block for receiving the measure generated by the detector and determining particular ones of the plurality of digital signal processing stages that are placed in a low-power non-operational state in conformity with the measure of amplitude or frequency, whereby in at least one operating mode, when the measure indicates that the amplitude of the input signal or the frequency of the input signal is below a threshold value, at least one but not all of the plurality of digital signal processing stages is placed in the low-power non-operational state, and wherein when the measure indicates that the amplitude of the input signal or the frequency of the input signal is above the threshold value, the at least one digital signal processing stage is placed in an operational state to provide a higher performance from the plurality of digital signal processing stages.

18. The integrated circuit of claim 17, wherein the plurality of digital signal processing stages implements at least one filter, and wherein the threshold value is predetermined such that an absolute image amplitude limit is enforced by permitting the at least one filter to have a lower amount of attenuation when the at least one of an amplitude or a frequency of the input signal is below the threshold value.

19. The integrated circuit of claim 17, wherein the plurality of digital signal processing stages comprises a plurality of interpolators coupled in cascade.

20. The integrated circuit of claim 19, wherein the plurality of digital signal processing stages comprises a sample rate converter that receives an input from an output of the plurality of interpolators.