Solid-state imaging apparatus
First Claim
1. A solid-state imaging apparatus comprising:
- a plurality of signal lines to each of which a signal is outputted from each of a plurality of pixels;
a plurality of first holding capacitors for holding the signal outputted from each of the plurality of signal lines;
a plurality of first CMOS switches arranged between the plurality of signal lines and the plurality of first holding capacitors, each of the plurality of first CMOS switches including a first NMOS transistor and a first PMOS transistor;
a first control line electrically connected to a gate of a plurality of the first NMOS transistors; and
a second control line electrically connected to a gate of a plurality of the first PMOS transistors, whereinthe first and second control lines supply signals of different timings, such that a timing of turning off the first NMOS transistor is shifted from a timing of turning off the first PMOS transistor.
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Accused Products
Abstract
Provided is a solid-state imaging apparatus comprising signal lines to each of which a signal is outputted from each of pixels, a first holding capacitor for holding the signal outputted from each of the signal lines, first CMOS switches arranged between the signal lines and the first holding lines, each of the first CMOS switches including a first NMOS transistor and a first PMOS transistor, a first control line commonly connected to the gates of the first NMOS transistors of the first CMOS switches, and a second control line commonly connected to the gates of the first PMOS transistors of the first CMOS switches, and signals of different timings are supplied to the first control line and the second control line such that a timing of turning off the first NMOS transistor is shifted from a timing of turning off the first PMOS transistor.
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Citations
11 Claims
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1. A solid-state imaging apparatus comprising:
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a plurality of signal lines to each of which a signal is outputted from each of a plurality of pixels; a plurality of first holding capacitors for holding the signal outputted from each of the plurality of signal lines; a plurality of first CMOS switches arranged between the plurality of signal lines and the plurality of first holding capacitors, each of the plurality of first CMOS switches including a first NMOS transistor and a first PMOS transistor; a first control line electrically connected to a gate of a plurality of the first NMOS transistors; and a second control line electrically connected to a gate of a plurality of the first PMOS transistors, wherein the first and second control lines supply signals of different timings, such that a timing of turning off the first NMOS transistor is shifted from a timing of turning off the first PMOS transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A solid-state imaging apparatus comprising:
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a plurality of signal lines to each of which a signal is outputted from each of a plurality of pixels; a plurality of first holding capacitors for holding the signal outputted from each of the plurality of signal lines; a plurality of first CMOS switches arranged between the plurality of signal lines and the plurality of first holding capacitors, each of the plurality of first CMOS switches including a first NMOS transistor and a first PMOS transistor; a first control line electrically connected to a gate of a plurality of the first NMOS transistors; and a second control line electrically connected to a gate of a plurality of the first PMOS transistors, wherein a first input pad for supplying a pulse to the first control line, and a second input pad for supplying a pulse to the second control line, wherein a delay quantity of the pulse from the first input pad though an electric path into a first NMOS transistor arranged closest to the first input pad among the plurality of first NMOS transistors driven by the first control line is different from a delay quantity of the pulse from the second input pad though an electric path into a first PMOS transistor arranged closest to the second input pad among the plurality of first PMOS transistors driven by the second control line. - View Dependent Claims (10, 11)
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Specification