Solid-state imaging apparatus

• US 8,582,003 B2
• Filed: 05/13/2011
• Issued: 11/12/2013
• Est. Priority Date: 05/21/2010
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Sakai, Seiichirou
• Primary Examiner(s): Tran, Nhan T
• Application Number:
  US13/106,946
• Publication Number:
  US 20110285893A1
• Time in Patent Office: 914 Days
• Field of Search: 348/241, 348/243, 348/248, 348/294, 348/300, 348/301, 348/308, 348/312, 257/292, 250/208.1
• US Class Current: 348/241
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

Provided is a solid-state imaging apparatus comprising signal lines to each of which a signal is outputted from each of pixels, a first holding capacitor for holding the signal outputted from each of the signal lines, first CMOS switches arranged between the signal lines and the first holding lines, each of the first CMOS switches including a first NMOS transistor and a first PMOS transistor, a first control line commonly connected to the gates of the first NMOS transistors of the first CMOS switches, and a second control line commonly connected to the gates of the first PMOS transistors of the first CMOS switches, and signals of different timings are supplied to the first control line and the second control line such that a timing of turning off the first NMOS transistor is shifted from a timing of turning off the first PMOS transistor.

Claims

1. A solid-state imaging apparatus comprising:

a plurality of signal lines to each of which a signal is outputted from each of a plurality of pixels;

a plurality of first holding capacitors for holding the signal outputted from each of the plurality of signal lines;

a plurality of first CMOS switches arranged between the plurality of signal lines and the plurality of first holding capacitors, each of the plurality of first CMOS switches including a first NMOS transistor and a first PMOS transistor;

a first control line electrically connected to a gate of a plurality of the first NMOS transistors; and

a second control line electrically connected to a gate of a plurality of the first PMOS transistors, wherein

the first and second control lines supply signals of different timings, such that a timing of turning off the first NMOS transistor is shifted from a timing of turning off the first PMOS transistor.

2. The solid-state imaging apparatus according to claim 1, wherein,

in all of the plurality of first CMOS switches, the first NMOS transistors turns off before turning off the first PMOS transistors, or the first PMOS transistors turns off before turning off the first NMOS transistors.

3. The solid-state imaging apparatus according to claim 1, further comprising

a control unit for controlling the signal to be supplied to the first and second control lines, such that the timing of turning off the first NMOS transistor is shifted from the timing of turning off the first PMOS transistor.

4. The solid-state imaging apparatus according to claim 1, further comprising

a plurality of second holding capacitors for holding a reset signal for resetting the pixel outputted from each of the plurality of signal lines;

a plurality of second CMOS switches arranged between the plurality of signal lines and the plurality of second holding capacitors, each of the plurality of second CMOS switches including a second NMOS transistor and a second PMOS transistor;

a third control line electrically connected to a gate of a plurality of the second NMOS transistors; and

a fourth control line electrically connected to a gate of a plurality of the second PMOS transistors, wherein

the third and fourth control lines supply signals of different timings, such that a timing of turning off the second NMOS transistor is shifted from a timing of turning off the second PMOS transistor.

5. The solid-state imaging apparatus according to claim 1, further comprising

a plurality of amplifier units arranged between the plurality of signal lines and the plurality of first CMOS switches, each of the plurality of amplifier units amplifying the signal outputted from each of the plurality of signal lines.

6. The solid-state imaging apparatus according to claim 1, further comprising

a first electrode pad for supplying a control signal to the first control line, and

a second electrode pad for supplying a control signal to the second control line.

7. The solid-state imaging apparatus according to claim 1, further comprising

an electrode pad, and

a delay circuit for delaying a signal inputted to the electrode pad, wherein

one of the first and second control lines is connected through the delay circuit to the electrode pad, and

the other of the first and second control lines is connected not through the delay circuit to the electrode pad.

8. The solid-state imaging apparatus according to claim 1, further comprising

a first input pad for supplying a pulse to the first control line, and

a second input pad for supplying a pulse to the second control line, wherein

a delay quantity of the pulse from the first input pad though an electric path into a first NMOS transistor arranged closest to the first input pad among the plurality of first NMOS transistors driven by the first control line is different from a delay quantity of the pulse from the second input pad though an electric path into a first PMOS transistor arranged closest to the second input pad among the plurality of first PMOS transistors driven by the second control line.

9. A solid-state imaging apparatus comprising:

a plurality of signal lines to each of which a signal is outputted from each of a plurality of pixels;

a plurality of first holding capacitors for holding the signal outputted from each of the plurality of signal lines;

a plurality of first CMOS switches arranged between the plurality of signal lines and the plurality of first holding capacitors, each of the plurality of first CMOS switches including a first NMOS transistor and a first PMOS transistor;

a first control line electrically connected to a gate of a plurality of the first NMOS transistors; and

a second control line electrically connected to a gate of a plurality of the first PMOS transistors, wherein

a first input pad for supplying a pulse to the first control line, and

a second input pad for supplying a pulse to the second control line, wherein

a delay quantity of the pulse from the first input pad though an electric path into a first NMOS transistor arranged closest to the first input pad among the plurality of first NMOS transistors driven by the first control line is different from a delay quantity of the pulse from the second input pad though an electric path into a first PMOS transistor arranged closest to the second input pad among the plurality of first PMOS transistors driven by the second control line.

10. The solid-state imaging apparatus according to claim 9, wherein,

the first input pad and the second input pad are formed by the same conductor pattern.

11. The solid-state imaging apparatus according to claim 9, wherein,

the first input pad and the second input pad are formed by the same conductor pattern;

the delay quantity of the pulse into the first PMOS transistor arranged closest to the second input pad is larger than the delay quantity of the pulse into the first NMOS transistor arranged closest to the first input pad.