System including memory stacks

• US 8,582,339 B2
• Filed: 06/28/2012
• Issued: 11/12/2013
• Est. Priority Date: 09/02/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US13/536,093
• Publication Number:
  US 20120268982A1
• Time in Patent Office: 502 Days
• Field of Search: 365/63, 365/51, 365/52, 365/200
• US Class Current: 365/51
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 29/812 using a reduced amount of fuses
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.

Claims

1. A memory system comprising:

a plurality of memory stacks, each memory stack including a plurality of memory circuits, wherein the memory circuits of the plurality of memory stacks are apportioned into one or more working memory sections and one or more corresponding mirrored memory sections; and

an interface circuit operable to;

communicate with the plurality of memory stacks and a memory controller, and

receive a triggering signal from the memory controller when the memory controller detects a data read error, wherein the interface circuit is configured to stop executing data read operations on at least one working memory section, and execute data read operations on at least one corresponding mirrored memory section, upon receiving the triggering signal.

2. The memory system of claim 1, wherein the plurality of memory stacks has an equal number of working memory sections and mirrored memory sections.

3. The memory system of claim 1, wherein a size of each working memory section is equal to a size of a corresponding mirrored memory section.

4. The memory system of claim 1, wherein, prior to receiving the triggering signal, the interface circuit is configured to:

receive data from the memory controller;

execute a first write operation to write the data to the at least one working memory section; and

execute a second write operation to write the date to the at least one corresponding mirrored memory section.

5. The memory system of claim 4, wherein, upon receiving the triggering signal, the interface circuit is configured to stop executing write operations on the at least one working memory section.

6. The memory system of claim 1, wherein, prior to receiving the triggering signal, the interface circuit is configured to execute data read operations only on the working memory sections.

7. The memory system of claim 1, wherein, within each memory stack, the plurality of memory circuits in the stack are apportioned between a working memory section and a corresponding mirrored memory section.

8. The memory system of claim 7, wherein, within each memory stack, the memory circuits apportioned to the working memory section are assigned a same address range as the memory circuits apportioned to the mirrored memory section.

9. The memory system of claim 1, wherein all of the memory circuits in a first memory stack are apportioned to a working memory section, and all of the memory circuits in a second memory stack are apportioned to a corresponding mirrored memory section.

10. The memory system of claim 1, wherein the interface circuit is operable to receive the triggering signal from the memory controller subsequent to a single-bit error or multi-bit error in data obtained from a memory circuit in the at least one working memory section.

11. The memory system of claim 1, wherein the interface circuit is operable to receive the triggering signal from the memory controller using side-band signaling.

12. The memory system of claim 11, wherein the side-band signaling is a System Management Bus (SMBus) signaling.

13. The memory system of claim 1, wherein the interface circuit is operable to receive the triggering signal from the memory controller using in-band signaling.

14. The memory system of claim 1, wherein the plurality of memory stacks are positioned on a dual in-line memory module (DIMM) and each memory circuit in each memory stack is an SDRAM circuit.

15. The memory system of claim 1, further comprising the memory controller, wherein the memory controller is operable to:

detect one or more data read errors occurring in at least one working memory section, and

generate the triggering signal upon detecting the one or more data read errors.

16. A memory system comprising:

a plurality of memory circuits, wherein the memory circuits are apportioned into one or more working memory sections and one or more corresponding mirrored memory sections;

an interface circuit operable to;

communicate with the plurality of memory circuits and a memory controller, and

receive a triggering signal from the memory controller when the memory controller detects a data read error, wherein the interface circuit is configured to stop executing data read operations on at least one working memory section, and execute data read operations on at least one corresponding mirrored memory section upon receiving the triggering signal.

17. The memory system of claim 16, wherein the plurality of memory circuits has an equal number of working memory sections and mirrored memory sections.

18. The memory system of claim 16, wherein a size of each working memory section is equal to a size of a corresponding mirrored memory section.

19. The memory system of claim 16, wherein, prior to receiving the triggering signal, the interface circuit is configured to:

receive data from the memory controller;

execute a first write operation to write the data to the at least one working memory section; and

execute a second write operation to write the date to the at least one corresponding mirrored memory section.

20. The memory system of claim 19, wherein, upon receiving the triggering signal, the interface circuit is configured to stop executing write operations on the at least one working memory section.

21. The memory system of claim 16, wherein, prior to receiving the triggering signal, the interface circuit is configured to execute data read operations only on the working memory sections.

22. The memory system of claim 16, wherein the memory circuits apportioned to the working memory section are assigned a same address range as the memory circuits apportioned to the corresponding mirrored memory section.

23. The memory system of claim 16, wherein the interface circuit is operable to receive the triggering signal from the memory controller subsequent to a single-bit error or multi-bit error in data obtained from a memory circuit in the at least one working memory section.

24. The memory system of claim 16, wherein the interface circuit is operable to receive the triggering signal from the memory controller using side-band signaling.

25. The memory system of claim 24, wherein the side-band signaling is a System Management Bus (SMBus) signaling.

26. The memory system of claim 16, wherein the interface circuit is operable to receive the triggering signal from the memory controller using in-band signaling.

27. The memory system of claim 16, wherein the plurality of memory circuits are positioned on a dual in-line memory module (DIMM) and each memory circuit in each memory stack is an SDRAM circuit.

28. The memory system of claim 16, further comprising the memory controller, wherein the memory controller is operable to:

detect one or more data read errors occurring in at least one working memory section, and

generate the triggering signal upon detecting the one or more data read errors.