Semiconductor device

• US 8,582,349 B2
• Filed: 08/24/2011
• Issued: 11/12/2013
• Est. Priority Date: 08/26/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun
• Primary Examiner(s): Lam, David
• Application Number:
  US13/216,562
• Publication Number:
  US 20120051119A1
• Time in Patent Office: 811 Days
• Field of Search: 365/149, 365/230.06, 365/189.05, 36518915-18917
• US Class Current: 365/149
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Abstract

An object is to provide a semiconductor device which includes a memory cell capable of holding accurate data even when the data is multilevel data. The semiconductor device includes a memory cell holding data in a node to which one of a source and a drain of a transistor whose channel region is formed from an oxide semiconductor. Note that the value of off-state current (leakage current) of the transistor is extremely small. Thus, after being set to have a predetermined value, the potential of the node can be kept constant or substantially constant by turning the transistor off. In this manner, accurate data can be stored in the memory cell.

Claims

1. A semiconductor device comprising:

a memory cell array including a plurality of memory cells arranged in matrix,

wherein one of the memory cells includes a node and a transistor,

wherein the transistor comprises a source, a drain and an oxide semiconductor layer,

wherein one of the source and the drain of the transistor is electrically connected to the node, and the other of the source and the drain of the transistor is electrically connected to a wiring,

wherein the oxide semiconductor layer includes a channel region, and

wherein the memory cell is configured to store data in the node in accordance with a signal applied to the wiring.

2. The semiconductor device according to claim 1, wherein the data stored in the one of the memory cells is multilevel data.

3. The semiconductor device according to claim 1, wherein the semiconductor device is mounted in an RFID.

4. The semiconductor device according to claim 3, wherein the RFID is provided in an object selected from the group consisting of a liquid crystal display device, an EL display device, a television receiver, a mobile phone, and a tag on a product.

5. A semiconductor device comprising:

a memory cell array including a plurality of memory cells arranged in matrix,

wherein one of the memory cells includes a node, a first transistor, a second transistor and a capacitor,

wherein the first transistor comprises a source, a drain and an oxide semiconductor layer,

wherein one of the source and the drain of the first transistor is electrically connected to the node, and the other of the source and the drain of the first transistor is electrically connected to a first wiring,

wherein the node is electrically connected to a gate of the second transistor and a first electrode of the capacitor,

wherein a second electrode of the capacitor is electrically connected to a second wiring,

wherein the oxide semiconductor layer includes a channel region, and

wherein the memory cell is configured to store data in the node in accordance with a first signal applied to the first wiring and a second signal applied to the second wiring.

6. The semiconductor device according to claim 5, wherein the data stored in the one of the memory cells is multilevel data.

7. The semiconductor device according to claim 5, wherein the semiconductor device is mounted in an RFID.

8. The semiconductor device according to claim 7, wherein the RFID is provided in an object selected from the group consisting of a liquid crystal display device, an EL display device, a television receiver, a mobile phone, and a tag on a product.

9. The semiconductor device according to claim 5, wherein the second transistor includes a semiconductor material other than an oxide semiconductor.

10. A semiconductor device comprising:

a memory cell array including a plurality of memory cells arranged in matrix;

a row decoder configured to select a given row of the memory cell array in accordance with a row address signal;

a column decoder configured to select a given column of the memory cell array in accordance with a column address signal;

a row address latch configured to hold the row address signal and to output the row address signal to the row decoder; and

a column address latch configured to hold the column address signal and to output the column address signal to the column decoder,

wherein one of the memory cells includes a node and a transistor,

wherein the transistor comprises a source, a drain and an oxide semiconductor layer,

wherein one of the source and the drain of the transistor is electrically connected to the node, and the other of the source and the drain of the transistor is electrically connected to a first wiring,

wherein the oxide semiconductor layer includes a channel region,

wherein the memory cell is configured to store data in the node in accordance with a signal applied to the first wiring, and

wherein supply of the row address signal to the row address latch and supply of the column address signal to the column address latch are performed through a second wiring.

11. The semiconductor device according to claim 10, wherein the data stored in the one of the memory cells is multilevel data.

12. The semiconductor device according to claim 10, wherein at least one of the row address latch and the column address latch is formed using a transistor whose channel region is formed from an oxide semiconductor.

13. The semiconductor device according to claim 10, wherein the semiconductor device is mounted in an RFID.

14. The semiconductor device according to claim 13, wherein the REID is provided in an object selected from the group consisting of a liquid crystal display device, an EL display device, a television receiver, a mobile phone, and a tag on a product.

15. A semiconductor device comprising:

a memory cell array including a plurality of memory cells arranged in matrix;

a row decoder configured to select a given row of the memory cell array in accordance with a row address signal;

a column decoder configured to select a given column of the memory cell array in accordance with a column address signal;

a row address latch configured to hold the row address signal and to output the row address signal to the row decoder;

a column address latch configured to hold the column address signal and to output the column address signal to the column decoder,

wherein one of the memory cells includes a node, a first transistor, a second transistor and a capacitor,

wherein the first transistor comprises a source, a drain and an oxide semiconductor layer,

wherein one of the source and the drain of the first transistor is electrically connected to the node, the other of the source and the drain of the first transistor is electrically connected to a first wiring,

wherein the node is electrically connected to a gate of the second transistor and a first electrode of the capacitor,

wherein a second electrode of the capacitor is electrically connected to a second wiring,

wherein the oxide semiconductor layer includes a channel region,

wherein the memory cell is configured to store data in the node in accordance with a first signal applied to the first wiring and a second signal applied to the second wiring, and

wherein supply of the row address signal to the row address latch and supply of the column address signal to the column address latch are performed through a third wiring.

16. The semiconductor device according to claim 15, wherein the data held in the one of the memory cells is multilevel data.

17. The semiconductor device according to claim 15, wherein at least one of the row address latch and the column address latch is formed using a transistor whose channel region is formed from an oxide semiconductor.

18. The semiconductor device according to claim 15, wherein the semiconductor device is mounted in an RFID.

19. The semiconductor device according to claim 18, wherein the RFID is provided in an object selected from the group consisting of a liquid crystal display device, an EL display device, a television receiver, a mobile phone, and a tag on a product.

20. The semiconductor device according to claim 15, wherein the second transistor includes a semiconductor material other than an oxide semiconductor.