Nonvolatile memory device

• US 8,582,353 B2
• Filed: 12/07/2010
• Issued: 11/12/2013
• Est. Priority Date: 12/30/2009
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Sung Yeon
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): HUERTA, PABLO S
• Application Number:
  US12/962,474
• Publication Number:
  US 20110157966A1
• Time in Patent Office: 1,071 Days
• Field of Search: 365/158
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits

Abstract

A nonvolatile memory device comprises a memory cell configured to store or output data in a magneto-resistance device in response to a write current applied to a bit line and a source line. A voltage detector is configured to sense potentials loaded in the bit line and the source line. A write current controller configured to control activation of a write control signal in response to an output of the voltage detector, and a write driver configured to control amounts of write current applied to the memory cell according to the activation of the write control signal.

Claims

1. A nonvolatile memory device, comprising:

a memory cell configured to write data in a magneto-resistance device in response to a write current applied to a bit line and a source line;

a voltage detector configured to sense potentials loaded in the bit line and the source line when a write enable signal is activated;

a write current controller configured to control activation of a write control signal in response to an output of the voltage detector; and

a write driver configured to control amounts of write current applied to the memory cell according to the activation of the write control signal.

2. The nonvolatile memory device according to claim 1, wherein the memory cell comprises:

a magnetic tunnel junction (MTJ) device coupled to the bit line; and

a switching device located between the MTJ device and the source line, the switching device having a gate coupled to a word line.

3. The nonvolatile memory device according to claim 1, wherein the voltage detector comprises:

a source line voltage detector configured to sense a potential of the source line when the write enable signal is activated, and configured to output a first detection signal and a first driving signal; and

a bit line voltage detector configured to sense a potential of the bit line when the write enable signal is activated, and configured to output a second detection signal and a second driving signal.

4. The nonvolatile memory device according to claim 3, wherein the source line voltage detector comprises a plurality of inverters coupled to the source line, each inverter having a different threshold voltage.

5. The nonvolatile memory device according to claim 3, wherein the source line voltage detector is configured to sense a voltage level range being smaller than a breakdown voltage and larger than a voltage level for writing a data of logic high level.

6. The nonvolatile memory device according to claim 3, wherein the bit line voltage detector comprises a plurality of inverters coupled to the bit line, each inverter having a different threshold voltage.

7. The nonvolatile memory device according to claim 3, wherein the source line voltage detector is configured to sense a voltage level range being smaller than a breakdown voltage and larger than a voltage level for writing a data of logic low level.

8. The nonvolatile memory device according to claim 1, wherein the write current controller is configured to inactivate the write control signal when the potential loaded in the source line is equal to and more than a breakdown voltage, and the write current controller is configured to activate the write control signal if the potential loaded in the source line is lower than a voltage level for writing a data of logic high level.

9. The nonvolatile memory device according to claim 1, wherein the write current controller is configured to inactivate the write control signal when the potential loaded in the bit line is equal to and more than a breakdown voltage, and the write current controller is configured to activate the write control signal if the potential loaded in the bit line is lower than a voltage level for writing a data of logic low level.

10. The nonvolatile memory device according to claim 1, wherein:

the write control signal comprises a first write control signal and a second write control signal; and

the write current controller comprises,

a source line current controller configured to output the first write control signal for controlling the amounts of write current provided to the source line in response to the output of the voltage detector; and

a bit line current controller configured to output the second write control signal for controlling the amounts of write current provided to the bit line in response to the output of the voltage detector.

11. The nonvolatile memory device according to claim 10, wherein the source line current controller is configured to operate only during operation of writing a data of logic high level.

12. The nonvolatile memory device according to claim 10, wherein the bit line current controller is configured to operate only during operation of writing a data of logic low level.

13. The nonvolatile memory device according to claim 1, wherein the write driver comprises a current source enabled by the write control signal so that the amounts of write current are adjusted.

14. The nonvolatile memory device according to claim 1, wherein:

the write control signal comprises a first write control signal and a second write control signal; and

the write driver comprises,

a first write driver configured to provide the write current to the bit line in response to the first write control signal; and

a second write driver configured to provide the write current to the source line in response to the second write control signal.

15. The nonvolatile memory device according to claim 1, wherein the write driver comprises:

a first current source configured to increase the amounts of write current when the write control signal is activated;

a second current source configured to decrease the amounts of write current when the write control signal is inactivated; and

a third current source configured to supply standard amounts of the write current when the write control signal is in a high impedance state.

16. A nonvolatile memory device, comprising:

a memory cell configured to perform data read or write operation in response to a write current applied to a bit line and a source line, wherein the memory cell includes,

a magneto-resistance device coupled to the bit line, and

a switching device located between the magneto-resistance device and the source line, the switching device controlled by a word line;

a voltage detector configured to sense potentials loaded in the bit line and the source line when a write enable signal is activated;

a write current controller configured to control voltage level of a write control signal in response to an output of the voltage detector; and

a write driver configured to control amounts of write current applied to the memory cell,

wherein amounts of current flowing through the memory cell are adjusted by the write control signal inputted to a gate of the switching device.

17. The nonvolatile memory device according to claim 16, wherein the magneto-resistance device comprises a magnetic tunnel junction (MTJ) device.

18. The nonvolatile memory device according to claim 16, wherein the switching device increase a current flowing in the memory cell when a voltage level of the write control signal increases and reduces a current flowing in the memory cell when the voltage level of the write control signal decreases.

19. The nonvolatile memory device according to claim 16, wherein:

the write current controller is configured to generate the write control signal having a lower level than a gate voltage of the switching device if the potential loaded in the source line is equal to and higher than a breakdown voltage; and

if the potential loaded in the source line is lower than a write voltage of data ‘

1’

, the write current controller is configured to output the write control signal having a higher level than the gate voltage.

20. The nonvolatile memory device according to claim 16, wherein:

the write current controller is configured to generate the write control signal having a lower level than a gate voltage of the switching device if the potential loaded in the bit line is equal to and higher than a breakdown voltage; and

if the potential loaded in the bit line is lower than a write voltage of data ‘

0’

, the write current controller is configured to output the write control signal having a higher level than the gate voltage.